FD-SOI Workshop Planned for San Francisco
The annual workshop on fully depleted silicon-on-insulator (FD-SOI) technology will be held on Feb. 24th in San Francisco, featuring technical presentations and discussions with experts in the field.
Presentation topics and speakers include:
• FinFET on SOI, by Terrence Hook of IBM
• Strain Options for FD-SOI, by Olivier Faynot of CEA-Leti
• Recent Advances in FD-SOI, by Bruce Doris of IBM
• Library and Physical IP Porting for FD-SOI, by Jean-Luc Pelloie of ARM
• Planar Fully Depleted Silicon Technology for Design Competitive SOCs at 28 nm and Beyond: Design Issues, by Philippe Flatresse of STMicroelectronics
• Planar Fully Depleted Silicon Technology for Design Competitive SOCs at 28 nm and Beyond: Technology Issues, by Michel Haond of STMicroelectronics
• 20 nm FD-SOI Models, by Brian Chen of Accelicon and the SOI Industry Consortium
• Enabling Substrate Technology for a Large-Volume Fully Depleted Standard, by Christophe Maleville of Soitec
• Advanced FD-SOI Design, by Bora Nikolic of the University of California-Berkeley
The 2012 Fully Depleted Workshop is scheduled for the day after the IEEE International Solid-State Circuits Conference (ISSCC), also held in San Francisco.
“Our goal with this workshop is to share the latest product design and processing advances in the FD ecosystem, thereby increasing the semiconductor community’s level of confidence in FD architectures,” said program co-chairman Horacio Mendez, executive director of the SOI Industry Consortium. “Each year, this event attracts hundreds of industry opinion leaders and key decision makers as SOI applications continue to gain momentum in high-volume markets.”
The workshop is organized by Mendez, Olivier Faynot, head of CMOS technology at CEA-Leti, and Carlos Mazure, chief technology officer of Soitec.
Registration is free.
Tags: FD-SOI, IBM, ISSCC, Soitec, STMicroelectronics