By Mark LaPedus, SemiMD senior editor

Moore’s Law is showing no signs of slowing down, but there are issues in the development of new mixed-signal designs: Analog is falling behind and remains a bottleneck in scaling.

Not long ago, chip makers simply developed a mixed-signal design by scaling both the analog and digital blocks on the same chip. But more recently, the mixed-signal world has seen a disconnect. Digital continues to scale at a frenetic pace, while analog trails the pack.

In the overall semiconductor scaling race, for example, the NAND flash crowd, namely Toshiba Inc. and SanDisk Corp., are shipping the world’s most advanced chips at 19nm. In contrast, the analog world is seeing a new rush of leading-edge design activity at 180nm. Analog has always lagged behind digital in scaling, but analog devices do not require leading-edge processes. The analog market is robust with a multitude of applications looming on the horizon.

But when scaling analog blocks with digital IP in mixed-signal designs, there are cases when the final chips “are bigger” — and have not shrunk — as compared to previous generations, said Navraj Nandra, senior director of analog/mixed-signal IP at Synopsys Inc.

“If you follow the rules of traditional scaling, (analog) does not scale,” Nandra said in an interview after a panel discussion at this week’s DesignCon in Santa Clara, Calif. “Analog can scale, but it requires new design techniques.”

Today, a growing number of overall IC designs are mixed signal products, according to Brian Bailey during the panel. Bailey, who runs his own firm called Brian Bailey Consulting, moderated the panel, entitled “Is it time for an analog comeback?”

But the problem is that “analog content in SoCs is decreasing as a proportion of the overall chip market,” said Warren Savage, president and CEO of IPextreme Inc., a supplier and licensor of semiconductor intellectual property (IP), during the panel. “Standard digital processes are (not optimized) for analog,” Savage said. “IP partnering costs are becoming prohibitive” in very deep sub-micron processes.

“We see a bright future for mixed-signal designs,” added Jeff Miller, director of product management at Tanner EDA, but “analog is a bottleneck. The process is totally different. (Analog scaling gets) harder and harder down the process nodes.”

The analog scaling bottleneck appeared to raise its ugly head at 90nm. The problems in analog scaling include parasitic effects, matching problems, well proximity effects, CD variance, antenna effects, mask misalignment, among others, he said during the panel.

“Some of these challenges are not new,” added Mladen Nizic, engineering director in the mixed signal unit within Cadence Design Systems Inc. “Suddenly, you now have to worry about power.”

To keep up in the mixed-signal world, new design techniques and architectures are required, said Synposys’ Nandra. “Analog IP can scale,” he said. “You have to design around the process rules for manufacturability.”

During a presentation, he listed three design techniques to help analog IP to keep up in scaling – at least in relative terms:

*Calibration techniques can be used to reduce demand on various analog features, such as gain, offset, matching, and increase robustness to PVT.

*Analog techniques can be implemented. For example, clock boosting circumvents low supply voltage. One can implement internal processing signals with large voltage swings.

*In another example, a CDR can be implemented in digital for a high speed Serdes design.

Tags: Cadence, IPexchange, Synopsys, Tanner EDA

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