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Piecing It Together
The move to 450mm wafers is under way, but nagging questions about ROI remain.…
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Mentor Musings
DFM processes are no longer optional. They are now required by manufacturers to create efficient, high-performance chips…
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Cascade Effects
Where do I know that guy from? And why is he here?…
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ASN's All Things SOI
Planar FD-SOI, FinFET, RF, memory and more—highlights of some great papers…
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Applied Innovation
President Obama Visits Applied Materials
Tour grabs national headlines as President speaks out on jobs and manufacturing.…
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The Foundry Files
The latest milestones and future trends for making MEMS a mainstream technology.…
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Semico Spin
Even ‘average’ is a good thing when it comes to wafer demand.…
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ImPatterning
Low-e Windows Built Using The Design Rules
How to create low e windows using design rules for the four energy bands.…
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Viewpoints: SEMI
Fab Equipment Spending To Rise
Strong 2nd half pulls 2013 finally into positive territory, 2014 growth in double digits.…
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Litho Guru
SPIE Advanced Lithography 2013 - day 4
The last day of the conference gave the tool updates. So how is EUV progressing?…
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Edges Of Darkness
Lessons From Past Architecture Wars
Why was Intel so successful when its very capable rivals were not? And can it maintain its lead?…
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Riding the Silicon Rapids
There's More To EUV Than Source Power
With a more powerful source, lithographers can use less-sensitive resists that are less prone to pattern collapse.…
- Trickle Down Equipment Economics
- Foundries Tip Hybrid FinFET Flows
- Capping Tools Tame Electromigration
- Challenges Mount For Interconnect
- Novellus Sees China, Wafer-Level Packaging, 3D NAND as Market Drivers
- Mike Clayton: Multi-beam direct write is decades off vs never, due to well documented roadblocks, in my opinion. EUV...
- Chris Schuermyer: I wonder what Noonen means by “20nm will be a fast ramp,”. Is that because of the ability to...
- mark: EV Group, Nanonex, MII, Obducat and Suss are among the players in the nanoimprint market. Some NIL vendors...
- Diogenes Cicero: Dr. Gotkis, The two statements in your note above are clearly not in “absolute...
- Kent Dahlgren: “Outside of programmable logic devices (PLDs), isn’t everybody of significance already using...
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FinFETs On SOI
What's changing at the leading edge of Moore's Law and why those changes are so important.
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Industry Research
Equipment Numbers Mixed For Q1
Year-to-year comparisons look dire everywhere but Taiwan, but sequential numbers look much better.
Mixed Signals
Following a disappointing period in the first quarter of this year, IHS plans to lower its chip forecast to 4.8% for 2013, down from 5.6% in the previous forecast.
Resource Center
White Papers
EUV Flare And Proximity Modeling And Model-Based Correction
EUV will introduce unwanted patterning distortions that must be accurately modeled and corrected.
Mask Data Preparation Flow For Advanced Technology Nodes
How to tame data file sizes, address fractured data files creation and streamline data review techniques.
Computational Lithography
Enabling 12 technology nodes in 12 years.
Next-Generation Signoff Analysis
Best practices for tackling electrical, physical and manufacturing challenges.
Optimizing Test To Enable Diagnosis-Driven Yield Analysis
Decreasing time to yield requires planning for what patterns to generate, what data to archive and hot to optimize your test program.
Calibre RealTime: Placing Signoff Verification into the Custom Designer’s Hands
A look at how to reduce custom/AMS design cycle time while improving design quality with on-demand, in-design signoff-quality verification.
A Call To Action: How 20nm Will Change IC Design
Double patterning marks a turning point in terms of lithography, variability and complexity.
Double Patterning From Design Enablement To Verification
A look at the challenges and various solutions using LELE at 20nm, including place and route effects, OPC and mask misalignment and image rounding.
Reducing IC Cycle Time With Calibre
Getting more functionality on the same die area using more and increasingly complex verification rules is getting more difficult. Here are some solutions.
EUV OPC For 56nm Metal Pitch
At 15nm and beyond, printing of pitches of 64nm and below will be required, and for EUV to replace ArF multi-exposure approaches patterns will have to be printed in a single-exposure process.















