Looking Past Silicon
By Ed Sperling
Silicon certainly isn’t going away, but most of the innovation in semiconductors won’t involve silicon in the future.
In a keynote speech today at the Industry Strategy Symposium in Half Moon Bay, Calif., IBM fellow Bernie Meyerson said that “we are in the end game” with silicon. “You are getting to the physical limit.”
This has implications for every facet of semiconductor design and manufacturing. The end of classical scaling at 90nm meant that for each new process shrink there would no longer be a guaranteed improvement in performance, power and a subsequent decrease in cost. None of those is guaranteed anymore by shrinking features, and the picture becomes even hazier after 11nm.
Going forward will require massive innovation in gate structures, new lithography technology, different materials and even greater innovation. Gate structures will move from FinFETs at 14nm to other approaches at future nodes. One such innovation IBM is experimenting with is gate-around nanowire. Another is CNTFET, or carbon nanotube FET, where channel lengths have been tested down to 9nm.
“The enormous challenge will be in manufacturing,” said Meyerson. “Silicon is not done, but we’re starting to look at non-silicon devices. There needs to be something else.”
Graphene is one alternative. So far, that has shown promise on a small scale, he said. Other elements in the Periodic Table are also under investigation, either alone or in combination.
Meyerson noted that IBM researchers now have the ability to manipulate single atoms, and have been using that capability to research the minimum number of atoms necessary to retain data in a magnetic memory bit. The number of atoms is 12. Anything less than that results in random data loss due to quantum effects.
The advantage of this approach is that memory chips can be dramatically smaller and density can be increased by as much as 10,000 times over RAM, or 160 times the density of flash, which changes the cost equation far more than a feature shrink.
Stacking die is another approach that can solve some problems, particularly performance limitations, by shortening the signal path between logic and memory. Meyerson said the speed of light is woefully insufficient for improving performance over distance, but shortening the distance in a stack can make up for that. “We’re going to see TSVs in logic sooner rather than later because of the system benefits,” Meyerson said.
One problem with stacked die is heat, however. Meyerson noted that by moving the I/O off the chip that heat can be significantly reduced. About half of the heat produced on a die is from I/O, he said.
In addition, there is value in utilizing research that already has been performed in different combinations. He said the deep integration of that research, other functions and systems requires innovation, as well, which can have effects across the board in IC design and manufacturing.
Tags: 3D stacking, carbon nanotubes, FinFETs, IBM