By Mark LaPedus, SemiMD senior editor

The rapid shift towards multicore microprocessors, newfangled FPGAs and other chips has paved the way for a new class of high-performance computers, mobile devices and other systems in the market.

Within these systems, there is a new and unforeseen set of demands piling up on the I/O, memory, software and other components. As in past years, bandwidth, power and performance remain a challenge in systems design.

But two other challenges are suddenly moving into the spotlight: Cache coherency and the ability to verify this technology. Cache coherency is critical, because it reduces latency and maintains the consistency of data stored in local caches within a shared resource.

“We have two kinds of things happening in the system: data processing and data transfer,” said Rajeev Ranjan, chief technology officer for Jasper Design Automation, an EDA vendor and developer of verification IP.

“Everybody has to access the memory. You also have to make sure the caches are coherent, but that’s become a bottleneck,” Ranjan said during a recent panel discussion. “Verification (ensures) that different components behave in a way that keeps the whole system coherent. So having comprehensive verification IP is very critical.”

Cache coherency, along with verification IP, are among the key enablers that will propel new designs in the market, including FPGAs. With these technologies, “we are ready to drive designs into a place where FPGAs haven’t historically gone,” said Dave Tokic, senior director of partner ecosystems and alliances for Xilinx Inc.

Over the years, the IC industry has moved to boost cache coherency and verification IP in system design – and for good reason. “The first cache coherency was built on a board and basically all of the devices were snooped on the addressed bus,” said Ashley Stevens, solutions architect at processor IP vendor ARM Holdings plc, during the panel. “Whenever there was a hit, you had to write data back to the memory and then read it again. That was very inefficient.”

Moving to solve the problem, ARM in June rolled out its latest AMBA 4 interface and protocol specification, which includes the AMBA 4 AXI Coherency Extensions (ACE). The AMBA protocol is an on-chip interconnect specification for the connection and management of functional blocks in a system-on-chip (SoC) design.

The technology enables system-level cache coherency across clusters of multicore processors based on ARM’s technology. AMBA 4 adds five new interface protocols: ACE for full cache coherency between processors; ACE-Lite for I/O coherency; AXI4 to maximize performance and power efficiency; AXI4-Lite and AXI4-Stream for FPGAs.

This builds on ARM’s previous technology, dubbed AXI3. “The big change is the addition of the ACE coherency extensions,” Stevens said. “The point of ACE is you don’t have to go back to memory. You can actually transfer data from processor to processor directly without going to memory.”

There is another and major key element to the technology: It deals with an age-old problem with cache coherency in systems based on multiple and disparate processors. “ACE allows you to share data between multiple processors and between processors and I/O devices,” he said. “In fact, the back story to ACE has finally come out, which is our ‘big.Little’ processing approach to multiprocessing, where we have the ‘Little’ Cortex A7 core cache coherent with the ‘big’ Cortex 15 core. We can switch between them according to the workload.”

Perhaps lost in the shuffle is another key element: Verification. “With AIX3, we produced our own verification IP,” he said. “But with ACE, (proprietary verification IP) isn’t going to work.”

Instead of going the proprietary route, ARM teamed up with Jasper. Jasper itself recently announced the availability of its suite of system-level verification IP for AMBA 4 ACE-based SoCs. Jasper’s VIP for ACE addresses hardware system-level issues such as absence of deadlocks and cache coherency.

Verification is a key part of the equation in designs like FPGAs. “The history of FPGAs is that you write some code, program it and put it on a bench. Then, you ask: Does it work? There wasn’t a lot of methodology behind the verification side of things,” Xilinx’ Tokic said. “In verification, if it was proprietary technology coming from multiple different vendors – and you were trying to stitch them together – you would simply fail.”

Earlier this month, Xilinx announced its first Zynq-7000 Extensible Processing Platform (EPP) shipments to customers. Based on a 28nm process, the Zynq-7000 family combines an ARM dual-core Cortex-A9 processor. The components on the device – an APU, memory interface unit, and the IOP – are all connected to each other through a multilayered ARM AMBA AXI interconnect. The interconnect is non-blocking and supports multiple simultaneous master-slave transactions.

The complexity of these and other types of devices will require robust hardware verification IP. “You have to make sure that all of these devices are compatible and are talking to the interconnect,” said Jasper’s Ranjan. “That in itself is a big challenge. Now you bring in the additional requirement that these devices are supposed to be coherent. That’s yet another verification challenge. There is one more challenge as SOCs become larger. Customers will create SOCs, which will have a multi-layer of interconnects. These are connected in a way that the whole system could potentially get into a deadlocked situation.”

As a result, verification IP vendors like Jasper must stay one step ahead of the curve. “In general, verifying hardware-based coherent systems is challenging for one reason. The problems take a long time to propagate to where you find the error,” said Ross Weber, a principal field application engineer with Jasper. With AMBA4, “we have been doing a lot of work to create a VIP for that and verify the protocol itself.”

Tags: ARM, Jasper, Xilinx

This entry was posted on Thursday, December 15th, 2011 at 10:45 am and is filed under Top Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.