By Mark LaPedus, SemiMD senior editor

As the industry has lowered its chip-testing costs over the years, IC test has been somewhat predictable. But in the emerging 2.5D and 3D chip era, IC test is entering the spotlight and the traditional test flow is under the gun.

In some circles, test is the biggest challenge to enable the 2.5D/3D chip era. The bottom line is that the industry must keep 2.5D/3D test costs at bay — or the technology won’t fly. “Test is going to be a huge challenge,” said Ivor Barber, director of packaging technology at LSI Corp., at a recent 3D chip panel. “Known-good-die (KGD) is also a real challenge.”

It seems like déjà vu, but the age-old problem of testing a key component in 2.5D and 3D designs — known good die, or KGD — has resurfaced again. Steve Pateras, product marketing director for Silicon Test Systems at Mentor Graphics Corp., said the industry will also require “new techniques” to test the silicon interposers with through-silicon-vias (TSVs), not to mention the 2.5D/3D chip designs themselves.

And in another critical piece of the test puzzle, there is a little-known debate brewing over a 3D design-for-manufacturing (DFM) or “design-for-test” (DFT) standard. Within the IEEE, a relatively new entity — the 3D Test Working Group — is hammering out a proposed standard called IEEE 1838. The proposed standard hopes to define the architecture and description language for the “test access” architecture within a 3D device. The test access architecture is critical, because it can be used to test and ensure the quality of a 3D device during the IC flow.

Now, the group is looking at two possibly rival test access technologies: One is based on the IEEE 1149.1 boundary scan standard, while the other is built around the IEEE 1500 embedded core architecture scheme. It is unlikely that the group will endorse both technologies. “For the moment, I think it’s preferable to have one standard,” said Erik Jan Marinissen, principal scientist at IMEC and chairman of the 3D-Test Working Group.

”IEEE 1149.1 and IEEE 1500 are not rivals,” Marinissen said. “They are two similar standards in neighboring domains. IEEE 1149.1 handles chips on boards, while IEEE 1500 handles embedded cores in SOCs. The two standards work perfectly together in many chip designs. The issue is: will we choose one or the other for a 3D die stack?”

Test gets no respect

For years, IC test has been a critical part of the flow. Not long ago, IC test costs were soaring out of control and the big functional logic testers were expensive and gigantic. But ATE vendors in recent times have moved to lower the cost-of-test by developing cheaper and more modular systems.

Still, there have been a multitude of ATE challenges over the years. For example, in the 1980s and 1990s, there was a big move to develop multi-chip modules (MCMs), which assembled or stacked several bare die devices within a substrate as a means to create smaller and faster systems. However, MCMs had limited success. One of the problems with MCMs was (and still is) to produce and test the bare die (KGD).

Like the MCM headaches of the past, the IC industry will face many of the same issues in the 3D chip era: How do you test and ensure the quality of KGD? And how do you test 3D chips in the first place?

Both 2.5D and 3D chips will require both traditional ATE and “non-conventional” test solutions, said Gary Fleeman, senior director of business development for ATE giant Advantest Corp. The bottom line is that “the cost of test can’t be more than the cost of yields,” Fleeman said.

To attack the problem, the IC industry is rethinking the overall test flow. The conventional test flow for today’s 2D chips includes IC manufacturing, wafer probe, packaging and final test. After a wafer is processed in a fab, it is placed on a wafer prober. A wafer prober is incorporated with a custom probe card, which itself has thousands of probing needles that hit the bond pads on each bare die — or KGD — on the wafer. Using electrical stimuli, the prober detects defective die, which are eliminated.

“Wafer probing is not really about testing the bond pads themselves; the bond pads are just an entry/exit point for test data that wants to test the circuitry inside the chip,” IMEC’s Marinissen said.

In some cases, the wafer prober is unable to detect all defective die. The needles sometimes miss the bond pads in some die or the contact force of the needles sometimes causes an issue with a die. In the 2D chip flow, the defective dies are sometimes caught when the parts are housed in IC packages and scrutinized during final test.

In 3D designs, however, there is a much greater requirement to find failures for the die — or KGD — during wafer sort and probe. Unlike 2D chips, 3D devices make use of stacked bare die. A defective die will cause a failure in the entire 3D device, meaning the part must be discarded.

As a result, the 3D test flow is far more complex and rigorous. For example, in 3D DRAMs, memory array devices will be stacked on top of a logic controller. The DRAM arrays may be produced by a memory house, while the logic and TSVs could be fabbed by a separate vendor.

Each fab vendor must test the separate memory and logic die, which is typically done on a wafer prober. Then, the logic and first level of memory arrays are partially stacked and tested via prober. Then, the process repeats itself.

But the high density of TSV interconnects has challenged today’s probe card architectures, thus limiting electrical test access. This in turn will require more and rigorous probe testing, said Eric Strid, chief technology officer for Cascade Microtech, a supplier of probe systems and probe cards. “You want very high test coverage at the die,” Strid said.

Wanted: New Solutions

To solve some of the limitations in probers, Cascade is developing the Microtech PA300PS 3D, which is said to be the world’s first probe station for electrical probing of 3D stacked structures on a wafer level. The semi-automated system is said to probe pads down to 25- x 25-micron.

Other solutions are emerging. Verigy, which was just acquired by Advantest, is talking about partial stack test. In this case, a probe card can be situated on the bottom or top of a device to test a partially stacked die. During a presentation at the recent Semicon Taiwan event, Verigy discussed a product called the picoAmpere Meter, which could be used in a new problem: TSV defects. The meter is designed for use in TSV parasitic measurements.

Still, there are more questions than answers in 3D chip testing. Mentor’s Pateras listed several questions, many of which still need to be addressed:

•How much probe does a 3D design need at the wafer level?

•How do you test a partial stack? How do you marry the tester interface to a partial stack?

•How do you test the interposers and TSVs?

If that wasn’t enough, Adam Cron, principal engineer at Synopsys Inc., listed another and oft-overlooked issue in the 3D design flow: “Physical handling (of the die or wafer) at the pre-stack stage and contacting TSVs in a high-volume manufacturing environment” could possibly cause defects.

While the industry wrestles with the hardware issues, vendors agree that DFM is critical for the enablement of 2.5D/3D chips. For some time, EDA vendors have offered tools based on hierarchical scan, built-in-self-test (BIST) and other DFM technologies.

A key and emerging DFT technology is the “test access port” within a design, which transports test data and control signals in the chip. Vendors are backing an assortment of different — and incompatible — test access schemes in 3D. In the 3D chip world, there is a pressing need for a standard test access architecture, said IMEC’s Marinissen. “If the dies come in from different sources, you need some DFT compatibility,” he said.

In 2010, the IEEE began to explore the need for a test access standard. This led to the formulation of a Project Authorization Request (PAR) in November 2010, entitled “Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits.” Earlier this year, the 3D-Test Working Group was officially hatched. And it moved forward on the so-called P1838 standard.

The standard will consist of two items: 3D test wrapper on-die hardware and a description language. The test wrapper is basically a generic test access to and between dies in a multi-die stack. The test access also includes “test elevator functionality,” which defines the path in which the signals need to be able to travel from the stack’s external I/Os and up and down through the stack.

Now, the question is whether the group will support one or both of the proposed standards. One proposed technology is based on the IEEE 1149.1 standard, which derived from boundary-scan technology. It was originally devised for testing PCBs using boundary scan.

The other proposal is based on the IEEE 1500 technology for embedded core test. One of the differences is the 1149.1 puts a “test access port” (TAP) controller on each chip die, while 1500 uses one centralized TAP controller.

The IEEE hopes to devise a standard by next year, but that’s easier said than done. Some companies have the roots in the 1149.1 world and are pushing that technology, while others are backing the 1500 technology. Some companies are already developing 3D products with their favorite technology in spite of a lack of standards. “Everyone has their own technology,” said Mentor’s Pateras. “That’s the problem.”

Tags: Advantest, IEEE, Imec, LSI, Mentor, Synopsys

This entry was posted on Monday, December 12th, 2011 at 3:36 pm and is filed under News Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.