IEDM: STMicro Adds TSVs, eDRAM to 28nm SOI CMOS
By David Lammers
STMicroelectronics presented its 28nm CMOS platform at the 2011 International Electron Devices Meeting (IEDM) in Washington, D.C. Tuesday (Dec. 6). The technology features ultra-thin-body fully depleted SOI with back-biasing techniques, embedded DRAM, and TSVs to provide wide IO connections to a DDR DRAM. It is based on a gate-first high-k/metal gate transistor technology developed at the IBM Semiconductor Development Alliance (ISDA) in Fishkill, N.Y., and features three threshold voltages to support various performance/power levels. It supports a 2 GHz processor speed and has a full range of analog/mixed-signal circuits.
“We are moving more toward high-performance applications in the mobile and wireless space, where there is less of a border between high performance and low power,” said program manager Franck Arnaud, who returned to Crolles, France to run the 32/28nm program after spending several years at the Fishkill, N.Y.-based ISDA.
STMicroelectronics has designed a 28nm SoC smartphone application processor that moves to prototyping in the second quarter of next year, he said.
The ultra-thin body biasing (UTBB) SOI technology takes advantage of forward and back biasing, using a back gate underneath the buried oxide layer which provides designers with dynamic Vt scaling technology (DVST). Because the channel is undoped and there is not a body factor, the backside gate works particularly well, he said. The Vt can be shifted by 100 mV at a 1V Vdd through the buried oxide layer of 25nm. There is no leakage through the bottom gate due to the 25nm thick BOX, he said.
“If you want to use the full capability of UTBB, designers have to shift their design style to that,” Arnaud said following his presentation. The back gate give designers an ability to tune the Vt’s at the device level and better support low-voltage operation, he said.
(Source: IEDM 2011, paper 15.7)
Compared with a finFET flow, the process is relatively simple. There is a cost to an SOI wafer (STMicro uses a wafer with a Si thickness [tsi]=7nm and box thickness [tBOX]=25nm). However, Arnaud said “the simpler process flow compensates for the wafer cost totally. There are fewer implant steps, for one thing.” Also, STMicro now has three SOI wafer suppliers that can meet the ultra-thin silicon spec: Soitec, SEH, and MEMC.
The 28nm platform includes an embedded DRAM technology running at 400MHz, based on a TiN/ZrO2/TiN capacitor. A cell size of 0.08mm2/Mbit support a high memory density, and the decoupled capacitor keeps costs down, he said.
STMicroelectronics is perhaps the first company to support a via middle 3D TSV technology for a SoC process flow. The vias have a diameter of 6um and a depth of 50um, and support 12.8Gb/s of bandwidth through a 512 bit bus running at 200Mhz to a DDR DRAM. There is no performance degradation of the surrounding logic block, which is sensitive to local noise and mechanical stress.
STMicro is among the first SoC vendors to offer a TSV technology.
In a separate IEDM paper, STMicroelectronics researchers reported a study of local noise, an increasing challenge at leading-edge design rules. They presented data showing the SOI technology is more immune to low noise degradation than a comparable bulk flow.
Tags: eDRAM, FD-SOI, Soitec, STMicroelectronics, TSV, UTB-SOI