By David Lammers

Intel Corp. researchers Wednesday (Dec. 7) said they have fabricated tri-gate InGaAs devices which show much better electrostatics than highly scaled planar InGaAs devices. For the first time, III-V tri-gate devices with a narrow fin width of 30nm showed better electrostatics — including sub-threshold swing (SS) and drain induced barrier lowering (DIBL) – compared with a III-V ultra-thin-body planar device with a highly scaled quantum well thickness (T_QW=10nm).

III-V channel materials are a hot topic at the 2011 International Electron Devices Meeting (IEDM), going on this week in Washington, D.C. As Intel, TSMC, GlobalFoundries and others plunge ahead with development efforts aimed at commercial production of vertical transistors, they have become relatively quiet about detailing their silicon finFET R&D efforts, for competitive reasons.

After two or perhaps three generations of silicon finFETs, however, companies may switch to higher-mobility channel materials, with III-V compounds expected for the NFETs and germanium, perhaps, for the PFET transistors.

With Intel embracing a tri-gate architecture for its 20nm silicon CMOS platform, it is no surprise that the company is hewing a vertical path in its III-V research. At IEDM, Intel researcher Marko Radosavljevic said InGaAs devices have an  effective velocity that is five times better than silicon, at the same DIBL. Though he called the III-V structures “experimental devices” which are far from optimized, they still have a 50 percent gain in Ion, at a matched Ioff, compared with silicon transistors. “If we extrapolate to a matched EOT and external resistances, there is an 80 percent gain at the same Ioff,” he said.

On Monday, Intel senior fellow Mark Bohr said Intel’s interest in III-V channels stems largely from their ability to operate at 0.5V or lower, which would reduce power consumption on Intel’s MPUs.

Radosavljevic said work remains to avoid the lattice mismatch between the buffer layer of Indium and the top device layer, which ideally would have a roughly 70 percent Indium content and about 30 percent Gallium. Now, the Indium content in the quantum well is limited to about 53 percent in order to match the buffer layer’s 53 percent ratio of Indium. While the high-k (EOT of 12 Angstroms) film was improved over last year’s IEDM presentation, Radosavljevic said “we can improve the electrostatics by using EOT scaling. If we scaled the gate dielectric to 8Å we would expect to see significant improvement.”

Intel created InGaAs devices on the same wafer, varying the fin thickness by creating 60nm, 45nm, and 30nm width fins. The narrower fins showed better electrostatics, better than the 10nm thick planar quantum well devices. “Tri-gate beats the 10nm planar ultra-thin-body devices,” he said during the Wednesday afternoon presentation.

The InGaAs devices have a gate length of 35nm. During the question and answer period, Thomas Skotnicki, an STMicroelectronics research manager who is a skeptic of the ultimate value of III-V channels, suggested that as Intel scales the gate length to what is needed for the 11nm or 8nm node it will find that the performance severely degrades. Radosavljevic defended the III-V work, suggesting that the improvements in electrostatics will continue as the gate length scales.

Purdue University graduate student Jiangjiang Gu, who studies under one of the best-known III-V researchers, Prof. Peide (Peter) Yu, presented work on InGa nanowires used in a gate all around (GAA) structure. “Indium gallium finFETs provide huge benefits as a function of the gate length,” Gu said.

The Purdue team created the III-V nanowires with a lithographically defined free-standing approach, rather than the “bottom up” approach of creating the nanowires. Atomic layer deposition was used for the GaOx conformal oxide. “Our nanowires were able to carry 140 microAmperes per wire, which is better than the state-of-the-art bottom-up nanowires.”

Gu said work remains to reduce the number of traps in the conducting layer, and to shrink the gate oxide. But he said the semiconductor industry will see “huge opportunities in gate-all-around III-V FETs.”

In an invited IEDM presentation on Tuesday, Imec research manager Marc Heyns outlined the challenges facing III-V device integration with Ge PFETs. The research community has been developing direct growth of both Ge and III/V materials in silicon STI trenches. The defects tend to move away from the active regions, in a phenomenon referred to as aspect ratio trapping.

“What do we have to do to make use of aspect ratio trapping. We have made exciting progress there. The epitaxial deposition of germanium is easy. With III-Vs, it is more difficult because each monolayer of As, As, Ga, and Ga, creates bonds with active defects,” Heyns said.

A second major challenge is the passivation of germanium, which he said may involve creating a monolayer of silicon on top of the germanium. “We need to make the interface thin, using special tricks. People prefer ALD instead of MBE for that, but we have to be careful about the interface defects,” he said, adding that antimony may be a candidate for the PFET channel. “Germanium is not the whole story,” he said.

Heyns concluded by predicting a fairly rapid introduction for III-V technologies. “I am convinced that in a couple of years we will see germanium and III-Vs in our computers.”

Tags: FinFETs, Germanium, GlobalFoundries, IEDM, III-V, Intel, TSMC

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