IBM Sees Performance from FD-SOI Transistors
By David Lammers
Fully depleted silicon on insulator (FD-SOI) devices are simpler to make and design with, and have equivalent performance and power metrics compared with bulk finFETs, IBM research manager Bruce Doris said, following a presentation at the recent IEEE SOI conference.
“In the past, there has been a lot of skepticism and controversy whether planar FDSOI could deliver performance. What we have shown is that these planar fully depleted SOI transistors are capable of the drive current needed for high performance applications,” Doris said, adding that the SOI community “not only wants low power, but they want some devices with high performance for smart phones and other systems.”
Ring oscillator results show a 20 percent performance improvement at a lower voltage (0.9V) for 20nm ETSOI devices, compared with 28nm bulk devices at 1V.
IBM and other leading semiconductor manufacturers have been considering the jump to bulk finFETs, which require close control of the patterning and etch fin-formation steps, as well a potential move to planar devices on SOI wafers with extremely thin silicon layers on top of a buried oxide (BOX). Startup SuVolta is offering a third alternative, licensing a bulk “deeply depleted channel” CMOS technology.
Doris declined to comment on IBM’s roadmap. Earlier this year, IBM vice president Gary Patton said that the Semiconductor Development Alliance, based at Fishkill and Albany, N.Y., is developing multiple technology options, including planar fully depleted SOI (which IBM refers to as extremely thin SOI, or ETSOI), and vertical transistors on both bulk and SOI substrates.
Doris said ETSOI devices resolve the problem of increased channel and halo doping required to scale bulk planar devices. The undoped channel in IBM’s ETSOI transistors avoids the random dopant fluctuation issue.
Bulk transistors face other challenges. The gate dielectric cannot be scaled much further without impacting the device’s electrostatics, and increased channel doping creates a junction between the source and drain which increases junction leakage. As scaling proceeds to the 20nm and beyond, bulk planar transistors also face increased drain induced barrier lowering (DIBL), which degrades control of the short channel.
At last June’s VLSI technology symposium, IBM researchers described performance metrics for high-performance and low-power ETSOI transistors. (Source: IBM)
IBM is considering the use of biasing techniques with the ETSOI devices, allowing performance boosts and power conservation as needed. He said multiple threshold voltages are straightforward, particularly compared with the hard-to-dope vertical transistors. Biasing and multiple Vt techniques are useful for low-cost mobile devices, and are easier to accomplish with ETSOI than with finFETs, he said.
Bulk planar transistors are running out of room for the stressors as devices scale to the 20nm node and beyond. Doris said IBM has developed techniques to strain the ETSOI transistors. Strain is an area where ETSOI technologists have been challenged by the finFET community, which argues that strain is difficult to accomplish with ETSOI devices. In an upcoming paper IBM plans to detail the performance gains seen from its strain techniques.
“For planar devices and finFETs on SOI, IBM has worked with Soitec researchers to show that we can use strained silicon created directly on the substrate. Without any embedded stress from outside we can get a lot of performance improvement from the strained channels,” he said.
“People are under the impression you cannot do strain with ETSOI,” he said. However, both planar and finFET devices in ETSOI technology gain performance from strained silicon. “The benefit is mainly to the nFETs; it will take a fair amount of work to get a good strain effect on the pFETs. One company is putting SiGe in the pFETs, and there is ongoing interest in a SiGe channel. There may be a good way to create a dual stress by using a strained substrate and SiGe,” he said.
Others have questioned whether ETSOI can be extended for several generations, given the need to use ever-thinner top layers of silicon. “ETSOI is not a one-node solution; it is scalable for several generations at tighter pitches. We have demonstrated that the thinner silicon works, particularly when we apply a voltage to the back side. It is capable of controlling the electrostatics,” he said.
In an upcoming EDL paper, IBM’s Ali Khakifirooz will present the latest performance results from scaled ETSO devices with the the silicon thickness as low as 3.5nm. (Source: IBM)
IBM has developed ETSOI transistors with substrates with Si thicknesses of 6, 5, and 4 nm, and will soon publish preliminary research on 3.5nm silicon in the IEEE Electron Device Letters journal, with Ali Khakifirooz as the lead author. “We think these are achievable in the timeline needed” to support devices with gate lengths in the 14-10nm range, he said.
“When we compared the 6nm channel with a 3.5nm channel, we saw electrostatic benefits and no performance degradation,” he said.
“There is plenty of thickness there (in the channel silicon), even at very thin films, to deliver as much current as needed. The thin silicon is not the thing causing the problems – there is higher resistance in the contact areas. When we look at the data, between the two different architectures (planar ETSOI and bulk finFETs) we don’t see a whole lot of difference in performance,” Doris said.
Doris highlighted results which compare a “state of the art” 28nm bulk planar transistor with a 20nm ETSOI planar transistor. The ETSOI device runs at a lower operating voltage (0.9 Vdd compared with 1.0 Vdd) while delivering a 20 percent performance boost and a 20 percent reduction in power consumption.
“We could have published from the same exercise at a .8V operating voltage, or even .7V,” adding that ring oscillator studies have been done at .8 Vdd.”
The SRAMs in particular benefit from not having dopants in the channel. Doris said they have much better stability than finFET transistors which require channel doping. “Structures without doping have much better SRAM stability. These ETSOI devices have no doping at all, so the random doping fluctuation that affects SRAMs is much better with ETSOI. We can get much lower voltages and the Vts are much better matched, with much less variability. There is dramatic improvement in the SRAMs,” he said.
“We believe the results we are getting are very technically impressive. We see smaller ground rules, a smaller footprint, and lower voltages, while consuming 20 percent less power. And the design porting challenge is much less with these planar devices compared with vertical transistors, which have a discrete width.”
The manufacturing challenges swing the argument in favor of planar ETSOI devices, he said. “In general, finFETs are seen as something very difficult to make. To control the electrostatics we need to make the fin thinner and thinner, and doing that on a vertical structure is very difficult. Up to now we have spent much of our time optimizing the gate, but finFETs force us to have fin features which are twice as small as the gate. One of the big challenges is controlling the silicon thickness. That is relatively easy if you get a flat surface to begin with.”
