By Mark LaPedus, SemiMD senior editor

Once upon a time, the DRAM server roadmap was predictable, as memory vendors simply marched down the natural progression of DDR interface standards.

Now, the DRAM server roadmap is muddled with both DDR and 3D chip schemes to address a major problem: The industry is scrambling for a new, low-power DRAM solution to help tackle the soaring bandwidth requirements — and power consumption rates — for servers in the datacenter. DRAMs provide fast data access times, but they are falling behind the I/O curve and require heat-generating refresh cycles.

DRAM vendors are shipping products based on the DDR3 interface standard and are gearing up for new, lower power DDR4 technology. Driving a wedge in the roadmap are the first 3D products based on through-silicon-vias (TSVs), which are supposed to boost the bandwidth speeds but lower power consumption.

Going 3D also dodges the perceived scaling limitations for DRAM, which may hit the wall at the 1xnm node. There are several and rival 3D-like DRAM technologies on the table: Hyper Memory Cube (HMC); high bandwidth, wide I/O, among others.

There are no clear-cut winners in the 3D DRAM race and the memory community is in somewhat disagreement about the DRAM server roadmap. But all server vendors are begging for a solution sooner than later. “We are going to need a paradigm shift,” said Ricki Dee Williams, senior principal hardware engineer at Oracle Corp., a database supplier that acquired workstation vendor Sun Microsystems in 2009.  “We are going to hit a memory wall.”

To stay on Moore’s Law, a server from Oracle/Sun must provide an off-chip bandwidth of 300 terabytes per second (Tbps) by 2020, up about 100x from today’s systems that operate from 2.5 to 5 Tbps. But to meet that target, there will be numerous power consumption, manufacturing and system challenges, he warned.

“Main memory bandwidth is limiting performance of future designs,” he said during a presentation at the JEDEC Memory Server Forum in Santa Clara, Calif. on Tuesday (Nov. 1).  “At the high end, the socketed DIMMs form factor needs to be replaced with direct attach 3D chip stacks supporting higher bandwidth memory interfaces.”

Art Kilmer, senior technical staff member for memory development for the Systems and Technology Group at IBM Corp., said power consumption and scaling are among the other concerns for multi-core, multi-threaded systems. “Technology scaling provides a means to reduce power while maintaining performance by lowering operating voltage,” he said at the JEDEC event. “However scaling will become exceedingly difficult beyond 2xnm processes.”

Data explosion

Indeed, the advent of the Internet has created an unforeseen explosion of data on the network. Internet traffic is expected to grow at a 32 percent compound annual growth rate from 2010 to 2015, but the power consumption rates within the datacenter are also climbing at an alarming rate, said Jim Elliott, vice president of memory marketing and product planning at Samsung Semiconductor Inc., during a presentation at the event.

One of the problems is the power-hungry server within the datacenter. The microprocessor used to be to the power hog in a system. Now, the DRAM shares the blame, as memory takes up “one-third of the power consumption in a server,” Elliott said.

Sherry Garber, an analyst with Convergent Semiconductors, a market research firm, said that soaring data — and power consumption rates — within the datacenter is not a new problem. The need for lower-power DRAMs for servers is also a constant. “The server people have been asking for a lower power solution since the 1990s,” Garber said. “That story has not changed.”

What has changed is the sense of urgency for the need of a new DRAM solution. “The most interesting thing (at the JEDEC event) is the level of frustration for the server guys,” she said. “The issue is DDR4, which will be introduced next year. They really want it” sooner than later.

The server and datacenter community is also clamoring for 3D DRAMs. “Products are being shipped, but TSV is expensive,” she added.

Indeed, for years, DRAM makers have been trying to close the bandwidth, I/O and power gap. In 2007, DRAM vendors rolled out products based on the DDR3 interface, which displaced the older DDR2 technology.

Samsung’s latest DDR3 DRAMs are based on 20nm-class processes and 1.35-volt technology. Vendors are readying 1.25-volt versions. In total, the shift from DDR2 to DDR3 represented a 67 percent reduction in power, Elliot said.

According to JEDEC’s roadmap, DDR3 now comes in two speed grades: 1,333- and 1,600-MHz. An 1,866-MHz version is also on the roadmap.  Following DDR3, Elpida, Hynix, Micron and Samsung are developing monolithic parts based on the next-generation interface — DDR4.

The first DDR4 DRAMs will come in 4-Gbit densities and 2xnm processes. The devices will operate at 2,133- and 2,400-MHz, which are slated for delivery in 2014 and 2015, respectively, according to the JEDEC roadmap. A 3,200-MHz and 16-Gbit version is due out in 2020.

Based on a 1.2-volt technology and a 16-bank architecture, DDR4 is expected to be about 30 percent to 40 percent lower power than DDR3. DDR4 also features VDDQ DQ termination, a 500,000 page size for x4 devices, new RAS features and error correction on the SODIMM using a common connector.

Also in 2014, the first 3D-based DDR4 chips are expected to appear in a 20nm, two-stacked configuration, according to the JEDEC roadmap. Four- and eight-stacked DDR4 versions are due out in 2016 and 2017.

Some JEDEC members are floating a 3D technology called high-bandwidth, which stacks DRAM on top of a logic device in a master-slave configuration. This is basically a server version of the so-called wide I/O memory scheme. Geared for handhelds, wide I/O DRAM is a four-channel, 128-lane technology said to enable a bandwidth of up to 12 Gbytes/s.

Roadmap debate

Samsung has other ideas about the DRAM roadmap. At the event, Jang Seok Choi, senior engineer at Samsung Semiconductor, presented a slide that tipped Samsung’s aggressive roadmap. As part of the plan, a 1.25-volt version of DDR3 would appear in 2011, followed by DDR3-based 3D TSV devices at 1,866-MHz in 2012, following by DDR4 in 2013.

There is a pressing need for DDR4 by 2013 “to keep server GB (per system density) with the same power budget,” Choi said. “TSV is also the right solution for servers” but “one of the challenges is cost.”

Last year, Samsung announced one of the first 3D TSV DRAMs, an 8-GB memory module based on DDR3. Last month, Samsung and Micron formed a consortium to develop a serial specification for a rival 3D memory technology called the Hybrid Memory Cube (HMC). Targeted for late 2013 or early 2014, HMC will incorporate DRAM arrays stacked on a logic chip.

At the JEDEC event, Kuljit Bains, a memory technologist at Intel Corp., had a slightly different viewpoint, saying DDR4  would remain the dominate DRAM technology at least until 2015 or 2016.

Some believe that DDR4 would run out of gas before then, but Bains disagreed. “We’ve been saying DDR would run out of gas for the last 10 years,” he told SemiMD, “but DDR4 is probably the last evolutionary technology” in the DDR roadmap.

Following DDR4, the DRAM market would most likely shift towards a newfangled 3D scheme, namely the so-called high-bandwidth technology. High-bandwidth would be slightly slower but would feature “lower power transistors,” he said.

Not surprisingly, the server vendors see another scenario. IBM’s Kilmer said “DDR4 capacity, power and bandwidth improvements over DDR3 are well aligned to server needs.”

Beyond DDR4, IBM is evaluating various 3D memory schemes. The shift to those schemes depends upon the “cost effective availability of 3D devices,” he said. “It’s a question of getting the yields for the silicon vias.”

Oracle’s Dee Williams said “DDR4 would take us to 2016, 2017, or maybe 2018,” with a 3D solution coming in the not-too-distant future. Oracle is exploring all options, such as MCMs, silicon interposers and 3D TSVs.

Like all server vendors, Oracle is also looking at the idea of stacking memory with the processor, but there are more questions than answers in the arena. “Stacking (memory) with CPU involves its own challenges,” he said. “How do we handle hundreds of amps and thousands of high-speed I/O delivered and dispersed throughout the stacks? How do we develop processes and methods to deal with a processor which sits on the top of the stack enabling heat sink attach/cooling?”

Tags: DRAM, IBM, Intel, Oracle, Samsung

This entry was posted on Thursday, November 3rd, 2011 at 3:39 pm and is filed under News Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.