FPGAs Move to New Transistors and 2.5D Stacks
By Mark LaPedus, SemiMD senior editor
Field-programmable gate arrays (FPGAs) are flexible, high-speed devices that have scaled in accordance with Moore’s Law.
FPGAs are not running out of gas, but they generally face some challenges in leading-edge designs. In some cases, there are I/O limitations, latency concerns and power issues when combining multiple FPGA devices in a system.
Xilinx ships 2.5D FPGA (Source: Xilinx)
So for these and other applications, FPGA vendors are looking to bring their products to the next dimension. For example, Xilinx Inc. Tuesday (Oct. 25) said it has begun shipping its previously-announced Virtex-7 2000T, a 2.5D stacked FPGA. The product is based on a 28nm process and a silicon interposer technology from Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC).
Rival Altera Corp. has yet to announce any products in the 2.5D or 3D arena, but it will soon reveal some details in the segment. But looking to upset the power of balance in FPGAs is Achronix Semiconductor Inc. and Tabula Inc.
Achronix, for one, will shortly ship its FPGAs not based on a 3D-like stacking technology, but rather built on a new, 22nm transistor architecture from Intel Corp. Last year, Achronix struck a deal under which Intel will provide foundry services for the FPGA startup. Intel’s 22nm process makes use of a tri-gate transistor technology – or FinFET.
Achronix' Robert Blake
With the tri-gate technology, “we will have a big performance advantage” over FPGAs based on 28nm technology, said Robert Blake, president and chief executive of Achronix, in an interview.
Over time, Altera and Xilinx may move to FinFETs. It’s unclear which newfangled FPGA technology will prevail in the market over time. The new FPGAs are geared for high-end markets and will likely carry a price premium.
While it is unlikely the newfangled architectures will displace the current FPGAs in the market, the new technologies could “open the door” for new markets and applications, said Rich Wawrzyniak, an analyst with Semico Research Corp.
And if proven successful, Xilinx’ 2.5D FPGA could serve as a technology and supply chain model for other chip makers to emulate, said E. Jan Vardaman, president of TechSearch International, a consulting firm.
It could also serve as a “springboard” for a range of new 2.5D FPGAs and non-FPGAs in the market, Vardaman said. What’s more, the adoption of 2.5D chips using interposers will likely “push out” the market for 3D devices based on TSVs, she said.
Sesh Ramaswami, senior director of strategy for the TSV program at fab tool giant Applied Materials Inc., said the 3D TSV chip market will take time to evolve due to costs. Initially, the market will first adopt 2.5D technology using silicon interposers, because the “cost is lower,” he said at a recent event.
Big steps
Still, there are several technical, supply chain and cost issues with 2.5D and 3D technology. Reliability, thermal problems, test and lack of EDA design tools are just a few of the issues.
“The design aspects for (2.5D and 3D devices) are not trivial,” said Girish Dixit, vice president of integration at chip-equipment maker Novellus Systems. Cost is another major concern, Dixit added.
Plus, there are only a few companies that can make fine-pitch interposers for leading-edge chips like FPGAs, Vardaman said. TSMC is perhaps the only foundry in the market with these capabilities, she said. “My concern is the (lack) of supplier base” that can provide fine-pitch interposers, she said.
GobalFoundries Inc. is expected to enter the 3D foundry business with both interposers and TSV technology. At a recent event, the company and Amkor Technology Inc. entered into a strategic partnership to develop integrated assembly and test solutions for advanced and stacked packaging solutions.
On the packaging side of the house, STATS ChipPAC is providing larger pitch interposers and TSV capabilities. ASE, Powertech and others will provide similar capabilities. Amkor said it does not plan to jump into the interposer or via creation business.
In any case, the next big thing in FPGAs is a series of new architectures. In March of 2010, startup Tabula launched the ABAX family of 3D programmable logic devices (3PLD). The products are based on its Spacetime architecture, which is said to dynamically reconfigure the chip on the fly. The device makes use of multiple layers or folds, which provides a certain function.
Tabula's 3D Programmable Logic Devices (Source: Tabula)
Achronix recently announced a deal under which the company would have its products made on a foundry basis by Intel. The FPGAs will be based on Intel’s recently-introduced 22nm technology, equipped with FinFETs, high-k dielectrics and other technologies.
Achronix’ Speedster22i FPGA family is said to have over 2.5 million LUTs in size, equivalent to an ASIC of over 20 million gates. The chips will provide as much as 300 percent higher performance, 50 percent lower power and 40 percent lower cost than any other FPGA, according to the firm.
The products will give Achronix a “three year lead” over the competition, Blake said, who added the company will shortly announce a shipment date for the products.
Liam Madden, vice president of FPGA Development and Silicon Technology at Xilinx, said the company is keeping a close eye on Achronix – and FinFETs. Altera is watching as well.
Both Altera and Xilinx use foundry services from TSMC. TSMC has announced a 20nm process based on a planar transistor architecture. The silicon foundry giant is expected to move to FinFET production at the 14nm node.
For its 2.5D FPGAs, Xilinx is using TSMC’s 28nm planar process and silicon imposers. The devices are built around Xilinx’ Stacked Silicon Interconnect technology, which combines passive silicon interposers with microbumps and through-silicon vias (TSVs) to enable FPGA die slices – or super logic regions (SLRs) – in a single package.
The 2000T FPGA is said to have 6.8 billion transistors. It consists of four FPGA SLRs mounted side by side on a passive silicon interposer, which itself is based on a 65nm process.
“The TSVs combined with controlled-collapse chip connection (C4) solder bumps enable Xilinx to mount the FPGA/interposer stack-up on a high-performance package substrate using flip-chip assembly techniques,’’ according to Xilinx. “The coarse-pitch TSVs provide the connections between the package and the FPGA for the parallel and serial I/O, power/ground, clocking, configuration signals, etc. “
For the parts, the microbumps, die separation and assembly processes are handled by Amkor. Xilinx does the final test. “We believe this is the correct (supply chain) model,” Madden said.
Still to be seen, however, is what Altera will do in the market. The company may provide a hint next month, at the upcoming RTI 3D conference. Altera’s Vice President of IC Engineering, Brad Howe, will be delivering a keynote at the event talking about the following subject: “Convergence of System Requirements Make Way for 3D Programmable Platforms.”
