Crossing Receives Order for 450mm Wafer Sorter

Crossing Automation Inc. (Fremont, Calif.) introduced its 450mm wafer sorter, the Spartan 450 and said it has an order for the new sorter from a semiconductor manufacturer. The platform is scheduled to ship in Q1 2012.

The Spartan 450 sorter incorporates features required to interface with a fab’s manufacturing execution system (MES). Initially targeting the 22nm technology node, it is extendible to 7nm technology, the company said. The 450mm sorter is designed as a single, integrated unit to enable faster installation and tool hookup, easier tool moves for increased flexibility, and a faster ramp to production, said May Su, vice president of marketing for Crossing Automation.

Share and Enjoy:

This entry was posted on Monday, September 26th, 2011 at 5:12 pm and is filed under Top Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.

Comments

Featured Video

Time For FD-SOI?

At the far end of Moore’s Law, the question is what will be the best solution for 20nm–fully depleted silicon on insulator or 3D transistors? The answer will likely include both.

Industry Research

Qualcomm, Micron, GlobalFoundries Gain in IC Rankings

Qualcomm, Micron and GlobalFoundries gained ground in the top 20 rankings in terms of sales in the first quarter of 2012, according to IC Insights. GlobalFoundries replaced Elpida in the top 20 rankings. The foundry vendor also jumped ahead of United Microelectronics Corp. (UMC).

Forecasters Boost Capital Spending Outlook

The IC business climate continues to improve in 2012, prompting various firms to raise their respective capital spending forecasts. Total semiconductor capital spending is now projected to hit $56.5 billion in 2012, nearly flat from the previous year and almost $6 billion higher than the January outlook, according to a new forecast from VLSI Research Inc.

More Industry Research

Resource Center

White Papers

Improving the Quality of PVD Cu Seed Layer

Authors from Novellus Systems and The University of Illinois describe how the quality of PVD deposited barrier/seed interface in copper interconnect metallization was significantly improved by enhancing Cu nucleation on the Ta surface.

Considerations for Porting a Bulk CMOS Design to FD-SOI

Technologists describe a straight port of an existing bulk CMOS design to
FD-SOI at the same node, obtaining the value of fully depleted SOI for a
modest redesign effort.

RF Substrate Technologies for Mobile Communications

Two Soitec Group managers — Eric Desbonnets and Stéphane Laurent — describe how SOI wafers support RF technology development.

Metric Pitch BGA And Micro BGA Routing Solutions

Via fanout and trace routing solutions for metric pitch ball grid array packages.

Design Impacts of Fully Depleted SOI

Xavier Cauchy, digital applications manager at Soitec, describes the design implications of fully depleted SOI technology at the 22/20 nm node.

Frequently Asked Questions About FD-SOI

Xavier Cauchy of Soitec and François Andrieu at LETI raise some of the technical issues surrounding fully depleted SOI technology. The authors compare FD-SOI to FinFETs, describe how non-digital transistors can be handled, and provide a list of references for further reading.

Manufacturing Closure with Calibre InRoute and Olympus-SoC

This Mentor Graphics paper describes the physical signoff challenges seen in advanced node designs.

More White Papers

Community