Intel’s Bohr Touts Tri-Gate for SoCs, Views 14nm
By Mark LaPedus, SemiMD senior editor
In a presentation at the Intel Developer Forum (IDF) in San Francisco, senior fellow Mark Bohr claimed that the tri-gate-based process will bring power and performance advantages to 22nm system-on-a-chip (SoC) products that planar transistors will not be able to match. Bohr also provided a glimpse of Intel’s 14nm process.
Already planning to ramp up production of its 22nm products this year, Intel is moving full speed ahead to develop a 14nm technology. Intel plans to build on its vertical tri-gate transistor structure at the 14nm node by extending the strained silicon and high-k/metal-gate schemes, said Bohr, Intel’s director of process architecture and integration. He provided few details about the 14nm process, however.
Other companies, including IBM, GlobalFoundries and TSMC, are pursuing finFETs for the 14nm node. Intel plans to begin ramping up its 14nm process by the fourth quarter of 2013, Bohr said, claiming that Intel will have a “four-year lead in tri-gate technology.”
Bohr reiterated the company’s position that extreme ultraviolet (EUV) lithography will not be ready in time for the 14nm node. Intel has said it plans to extend traditional 193nm optical lithography down to 14nm, with the help of multiple patterning and other techniques.
“We would like to use EUV, but it’s not ready,” Bohr said in an interview, adding that “I’d like to have EUV” ready for the 10nm node.
Intel’s 22nm SoC Process
Bohr discussed Intel’s SoC process recipes for the 22nm node, a critical weapon in Intel’s effort to gain share in the smartphone space. In previous years, Intel developed a standard “one-size-fits-all” CPU process technology for a particular node.
Starting at the 32nm node, Intel developed a CPU (P1268) and an SOC (P1269) process. The CPU and SoC processes have identical feature sets, but the SoC version incorporates a superset of features optimized for SoC designers.
For example, Intel will provide a standard CPU process at 22nm, internally called P1270. Based on a tri-gate transistor structure, the CPU process incorporates high-speed logic circuits and interconnects.
The SoC version, dubbed P1271, makes use of a low leakage technology, dense interconnects and passives. It will also include 1.2V low-power and 1.8V thick-gate options.
Dick James, a technology analyst at ChipWorks, the Canadian reverse-engineering firm, said he believes the SoC process will roll out in Intel products sometime in 2012.
Intel will provide four SoC process flows or recipe options for designers: high-performance, standard performance, low power and ultra low power, according to Bohr.
The SoC technology is aimed at a range of applications, including the mobile space. Intel is seeking to propel its x86-based processors in the mobile space, and displace the ARM-based products in the process.
Bohr said Intel’s tri-gate transistor, rolled out in May, represents a fundamental departure from the two-dimensional planar transistor structure. The first tri-gate-based processor, code-named “Ivy Bridge,” is slated for high-volume production by the end of this year.
Bohr said Intel’s tri-gate structure enables a “10X reduction in leakage” over planar devices. Compared to tri-gate structures, ‘’22nm planar transistors would provide only a modest improvement in delay versus voltage,’’ he said, arguing that “tri-gate transistors provide an unprecedented 37 percent delay improvement at low voltage,’’ as compared with 32nm planar structures.
Intel’s first 22nm processor, called Ivy Bridge, is mainly geared for desktops and possibly higher-end notebooks. The next 22nm processor is code-named Haswell, which is tailored for Ultrabooks. Developed by Intel, Ultrabooks is a new class of portables that are aimed at the tablet PC market.
At IDF, Intel described the new class of platform power management in development for the 2013 “Haswell” products for Ultrabooks. Haswell will reduce idle platform power by more than 20 times over current designs, according to Intel.
















