Older Nodes, Newer Process Technology
By Ed Sperling
Competition in semiconductor manufacturing has always been intense at the leading edge, but it’s now also heating up at older process nodes.
While it’s extremely difficult to compete with the likes of GlobalFoundries, Samsung, TSMC and Intel at 28nm and 22/20nm, where the investment in equipment and the manufacturing process can be measured in billions of dollars, the cost to build and fully equip fabs at 65nm and beyond is measured in millions. That significantly changes the ROI equation, particularly when mainstream is still being defined as 55nm and older nodes.
“Over the last few years we’ve seen the volume remain at 65nm,” said Walter Ng, vice president IP ecosystems at GlobalFoundries’ IP, during a panel discussion yesterday at the Global Technology Conference. “But there are a lot of companies doing things that are very relevant today even at 0.25 (microns).”
GlobalFoundries isn’t alone in spotting this trend. “Even though it’s sexy to talk about the leading edge, about 75% of ARM’s royalty comes from cores developed in 2006 and earlier,” said John Heinlein, vice president of marketing for the physical IP division at ARM.
ARM's Heinlein: Mainstream is 55nm and older.
The reasons are almost entirely economic, and they are fostering debate about the continued relevance of Moore’s Law beyond 20nm. That’s not to say the most advanced process nodes are wanting for customers or technology. But there are fewer customers at 28nm and 22nm than there were at 65nm, and the trend points to even fewer chips being designed at future nodes. Moreover, while chipmakers used to move from one process node to the next every two to three years, that is no longer a requirement. Even the most advanced devices have a mix of chips from different process technologies because the volume of chips needed to recoup design and production costs increases at each new process node—and at 14nm it’s hard to imagine many markets that can sustain the necessary volume.
These changes haven’t been lost on a handful of new startup foundries in places like China and Singapore, which see a successful business at older process nodes. In fact, the race for this part of the market has spawned a renewed interest in beefing up some of the technology, particularly when it comes to power and high performance. At 130nm, power was considered an afterthought, for example. But now that these chips are being combined with other semiconductors developed at the leading-edge processes, even they have to be retrofitted to deal with power issues at the architectural stages.
“If you have an existing product, you can look at adding oscillators or an EEPROM developed at an older node to reduce the system cost,” said Jeff Lukanc, director of engineering at IDT. “You have to look at the economics of the lower cost. It’s not always a slam-dunk, but if you look at mixed signal design and RF design, at the leading edge nodes it’s really tough.”
This will become critical in stacked die, where multiple die are thinned out and then stacked together. Power budgets need to be developed for the entire 3D package, not just a single die, so every component needs to be as power-efficient as possible.
“There’s a point at which a heterogeneous multichip package will become attractive,” Lukanc said.
When exactly that happens no one is certain, but foundries and design services companies say they are now creating demonstration chips that will be used in stacked configurations, and memory companies have announced stacked-die packages that are expected to be integrated with logic chips starting in 2012 through an interposer layer or using through-silicon vias.
Tags: 3D stacking, ARM, GlobalFoundries, IDT