Novellus Sees Three-Dimensional Future
by Katherine Derbyshire
If a single thread runs through Novellus’ announcements this year at Semicon West, it’s the increasingly three-dimensional nature of device structures. From FinFETs and advanced memory to stacked chip structures, it’s clear that the semiconductor world is no longer flat.
On the transistor process side, there has been some debate about the choice between fully-depleted silicon-on-insulator (FD-SOI) devices and FinFETs, with Intel landing firmly on the side of FinFETs. Intel claims that its FinFET process is only 2-3% more expensive than a comparable planar transistor process. On the other hand, IC Knowledge recently completed a cost analysis — in collaboration with Soitec — which found only a 1% cost difference between fully-depleted SOI devices and a comparable planar CMOS process on bulk wafers. IMEC Executive VP Ludo de Ferm suggested that both arguments may be correct: the costs of the two approaches are so similar that the most cost-effective technology ultimately depends on the application.
Girish Dixit, Novellus VP for process applications, observed that his company’s processes can be used with either planar or FinFET devices. To make FinFETs, however, manufacturers will need to deposit highly conformal dielectrics onto complex vertical structures. Dielectrics are used as spacers, as sacrificial layers in double-patterning schemes, even as diffusion sources for sidewall doping. Such conformal depositions are often seen as a natural market for atomic layer deposition. Unfortunately, as Dixit pointed out, ALD is slow and requires relatively high temperatures, usually above 400º C. Particularly in second-generation FinFETs, even minor temperature perturbations are likely to change the junction shape or dopant concentration. In some double-patterning schemes, depositing a dielectric spacer directly onto photoresist could allow the fab to eliminate one lithography and one etch step, substantially reducing the process cost. However, such a scheme would require a dielectric deposition temperature below 100º C.
To address these issues, at Semicon West Novellus announced the VECTOR CFD family of films for the company’s plasma-enhanced chemical vapor deposition (PECVD) systems. The suite includes oxide, doped oxide and nitride films that are deposited at temperatures ranging from 50º to 450º C, with throughput as high as 80 wafers per hour (for CFD oxide). These films provide solutions for a wide range of applications, including not only FinFET and double-patterning spacers, but also bitline spacers, etch stop layers, resistor protect layers, and through silicon via (TSV) dielectric liners.
Conformal oxide deposited over FinFET core by Novellus Vector CFD. Image courtesy of Novellus
No matter what transistor structures eventually emerge, they will need contacts to connect them to the rest of the circuit. Narrow, high-aspect ratio contacts present process problems of their own. Deposition of the barrier layer and contact material narrows the contact opening, threatening to pinch it off before complete fill is achieved. The ExtremeFill Tungsten process, also announced at Semicon West, uses an additional step to widen the opening, allowing complete fill with no voids.
Meanwhile, on the interconnect side, copper resistivity is becoming a major issue. High performance chips have lots of short connecting lines, in which the diffusion barrier layer consumes a substantial fraction of the total cross section. Novellus and Tokyo Electron are working to develop and integrate high coverage processes with alternative barrier layer materials. According to results presented by Rohan Akolkar and colleagues at this year’s IEEE Interconnect Technology Conference, the introduction of copper-complexing agents into the plating bath substantially improves copper nucleation on ruthenium, allowing direct plating of copper onto ruthenium. Novellus’ DirectSeed technology gives a 5-7% reduction in interconnect resistivity, Dixit said. No product has been announced yet, pending the results of customer integration studies.
Tags: contacts, copper interconnects, FD-SOI, finFET, FinFETs, IC Knowledge, Imec, Intel, Novellus, PECVD, Soitec, Tokyo Electron Ltd.