The Challenge of 3D
Juan Rey, senior director of engineering for Mentor Graphics’ Design To Silicon Division, talks about 3D stacking and 3D structures on chips.

Tags: Mentor
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Deep Insights for Chip Builders
The move to 450mm wafers is under way, but nagging questions about ROI remain.…
DFM processes are no longer optional. They are now required by manufacturers to create efficient, high-performance chips…
Planar FD-SOI, FinFET, RF, memory and more—highlights of some great papers…
The latest milestones and future trends for making MEMS a mainstream technology.…
Even ‘average’ is a good thing when it comes to wafer demand.…
Low-e Windows Built Using The Design Rules
How to create low e windows using design rules for the four energy bands.…
SPIE Advanced Lithography 2013 - day 4
The last day of the conference gave the tool updates. So how is EUV progressing?…
Lessons From Past Architecture Wars
Why was Intel so successful when its very capable rivals were not? And can it maintain its lead?…
Fab Equipment Spending To Rise
Strong 2nd half pulls 2013 finally into positive territory, 2014 growth in double digits.…
There's More To EUV Than Source Power
With a more powerful source, lithographers can use less-sensitive resists that are less prone to pattern collapse.…
President Obama Visits Applied Materials
Tour grabs national headlines as President speaks out on jobs and manufacturing.…
Juan Rey, senior director of engineering for Mentor Graphics’ Design To Silicon Division, talks about 3D stacking and 3D structures on chips.

Tags: Mentor
This entry was posted on Wednesday, July 6th, 2011 at 6:23 pm and is filed under Podcasts Videos Webcasts, Technology Features. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.
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