By David Lammers

Now that Intel Corp. and TSMC have publicly committed to finFETs at the 22nm and 14nm nodes, respectively, attention is turning to what the next moves will be from the ultra-thin-body SOI camp.

At the recent Symposium on VLSI Technology, held in Kyoto, Japan, a 22nm technology platform based on extremely thin SOI substrates was presented, with a 25 percent improvement in ring oscillator speed compared with a 28nm bulk transistor. The presentation from a team based in Albany, N.Y. (IBM, STMicro, GlobalFoundries, Renesas, and Toshiba) included analog devices and SRAMs with a 0.08 square micron cell size.

A faceted raised source-drain design reduced parasitic capacitance. And the researchers said the undoped channel in ETSOI “greatly reduces the random dopant fluctuation, a major source of device variation.”

The competition between finFETs and the planar ultra thin body SOI is the subject of a TechXPOT at Semicon West on Tuesday, July 12^th, beginning at 10:30 a.m. The two-hour Emerging Architectures for Logic and Memory session includes presentations from Serge Biesemans, vice president of process technology at Imec, on FinFETs; Ali Khakifirooz,  ETSOI lead device engineer at IBM Research, on the ultra thin body SOI approach; and Raj Jammy, vice president of materials and emerging technologies at Sematech, on the heterogeneous integration of high mobility Ge/III-V channels on silicon.

This week, several of the SOI wafer suppliers, including MEMC, SEH, and Soitec, said they are ready to supply the UTB-SOI wafers in high volumes. To support a fully depleted transistor, the critical silicon layer must be kept to 10 nm or less, with minimal variations. Because the cost of the wafers is partially offset by a less-expensive isolation process, the SOI Consortium is claiming no overall increase in the cost of a processed UTB-SOI wafer compared with bulk silicon.

The wafer suppliers in part are responding to comments made by Intel senior fellow Mark Bohr in early May, when Intel rolled out its 22nm finFET-like tri-gate technology. During the press conference, Bohr said Intel’s finFET process cost was just a few percent higher than its planar technology. “Those extremely thin (silicon and BOX layer) SOI wafers are available, but they are very expensive, and pretty hard to get,” Bohr said. He said Intel’s estimate is that using a thin-layered SOI wafer would add 10 percent to the finished wafer cost.

Those assertions riled executives at the SOI wafer suppliers, who have invested in facilities to make the SOI wafers in volumes, sufficient to meet demand from companies making chipsets for smart phones and other mobile systems.

Christophe Maleville, general manager of  Soitec’s microelectronics business unit, said Soitec has an installed industrial base of 2 million wafers per year at its two 300-mm SOI wafer production fabs in Bernin, France and in Singapore.  “We are prepared to expand our SOI capacity to accompany the introduction of FD-SOI technology in very high-volume consumer applications,” Maleville said.

The “Xtreme SOI” wafers from Soitec have “Angstrom-level uniformity, using the same technology platform as our large-volume current production,” Maleville said.

Soitec has licensed its Smart Cut SOI wafer-production technology to Shin-Etsu Handotai (SEH), the largest wafer supplier worldwide, and SEH has completed development of its UTB substrates. Noburo Katsuoka, director of the SOI program at SEH, said “SEH is delighted to deliver the products on request.”

MEMC, based in St. Louis, has been a second source to IBM for the SOI wafers it uses for its partially-depleted CMOS production. Shaker Sadasivam, president of MEMC Semiconductor Materials, said, “MEMC is ready to facilitate and encourage the faster adoption of fully depleted SOI for mobile applications. Large volume utilization is a key factor to achieve reduced pricing for FD SOI, and MEMC has capacity that can be readily expanded to meet industry needs for volume production.”

Sadasivam added that “plans have been developed to expand our FD SOI production to approximately 45,000 wafers per month.”

Horacio Mendez, executive director of the SOI Industry Consortium, said some high-volume mobile IC vendors may introduce fully depleted SOI technology before the 14/15nm node, though FD-SOI will “come in at full force at 14 nanometers.”

A key demand from the mobile IC providers is to have multiple wafer vendors, partially in order to gain lower wafer costs. Soitec has committed to $500 per-wafer pricing in volumes for FD-SOI wafers.

The SOI consortium has been working with a fairly large team of engineers from ARM Ltd. to prove out the advantages of FD-SOI at the 22nm node, Mendez said. Further information about that development project will be made public later this summer, he said.

Mendez said he strongly disagrees with Bohr’s assertion that FD-SOI will add 10 percent to the cost of a planar CMOS silicon process. Because the implant and isolation steps are so much simpler with an SOI substrate, the SOI Consortium believes the finished cost of an SOI wafer will be about 6 percent less than a bulk silicon wafer.

“At 20nm, the performance of a fully depleted technology is so good that companies feel they don’t need to add the stressors, saving on costs there,” said Mendez, a former MPU designer at Freescale Semiconductor.

While Intel may have the manufacturing muscle to implement its tri-gate technology, Mendez said there are few other companies that will be able to make finFETs at good yields. “The yields on finFETs have to be challenging. At the beginning, companies will run into rough patches, where they will not see the same yields as planar transistors,” Mendez said.

One thing the SOI Consortium and Intel agree on: bulk silicon CMOS “is not going to cut it past the 22nm node,” he said.

Tags: MEMC, SEH, Semicon West, Soitec, UTB-SOI

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