The Future Of Memory
By Ed Sperling
Future memory technology inside of mobile devices will use less power and run faster at each rev of Moore’s Law, but that technology also will look different, use different materials, and will be manufactured with different equipment, processes and technologies.
While this technology will owe its heritage to research and testing of the past few decades, the differences are expected to be dramatic. A panel of vendors, their customers and researchers took a deep dive into the research that will change the memory market of the future at an IEEE International Memory Workshop held Monday in Monterey, Calif. The discussion, chaired by Raman Achutharaman, VP of strategy and marketing for Applied Materials’ silicon systems’ group, pointed to some interesting research, developments and future standards.
What’s next?
Laith Altimime, Imec’s program director for CMOS process technology, said that over the next decade memory makers will require new materials (graphene and/or carbon nanotubes, for example); new techniques, including EUV lithography, air gap insulation and 3D stacking with through-silicon vias; and new structures, including hybrid tunneling field effect transistors (TFETs), VFETs and TANOS cells.
“New materials and device architectures are the key,” said Altimime, noting that 3D stacking will “take over everything in its path.” That includes resistive RAM (RRAM), a non-volatile type of memory now in the research phase that relies on current applied to a filament; 1T-RAM, a higher-density version of RAM; and spin-transfer torque RAM, which changes the magnetization on a thin magnetic layer by running a spin-polarized current across it.
Altimime noted that scaling beyond 16nm most likely will require 3D cell architectures. He said the base material will still be CMOS, but it also will include higher-k dielectrics, metals, and stack engineering.
Fig. 1: Air gap insulation. Source: Applied Materials
NAND changes
Sung-Kye Park, of Hynix’s Memory R&D Division, noted that NAND will require a slew of changes to decrease charge loss and increase e-field retention. Those changes will include everything from air gap technology to an increased doping of the control gate. He expects new structures and new materials to start hitting the market within two years.
“3D flash is a possible candidate,” Park said, pointing to Toshiba’s pipe-shaped Bit Cost Scalable technology, Samsung’s Terabit Cell Array Transistor (TCAT), Hynix’s 3D-FG and hybrid chips. But he noted there also are potential hurdles in areas such as process integration, particularly in the areas of multistack deposition and word-line formation.
Fig. 2: 3D NAND architectures. Source: Applied Materials
DRAM shift
Joo Young Lee, strategic planning manager at Samsung, said the goal for DRAM is still a 35% cost reduction each year, but to achieve that will require moving to the next process nodes. DRAM is currently approaching 30nm, he said. He expects it to hit 25nm by 2015 and 14nm by 2020, with DDR4 hitting mainstream in 2013. EUV will be required at 14nm, he said.
Reaching those advanced nodes will require changes in some of DRAM’s basic structures—cell capacitors, cell array transistors and cell node contacts, all of which will need to be re-engineered.
Patterning issues
Yoshitaka Tsunashima, a leading researcher at Toshiba, said his company’s NAND technology already requires double patterning. At 14nm, double patterning and EUV both will be required.
EUV has its own issues, of course—light source performance, mask defect control, optical performance, mask data preparation, and resist performance. But he noted that 11 companies are now working to solve those issues as part of the EUV Infrastructure Development Engineering Center (EIDEC).
“The other way we can get there is 3D NAND,” he said, noting that either approach—lithography or stacking—or both will help reduce bit costs. He said that technology also can be extended to RRAM, organic memory and MEMS memory.
Customer view
Nokia’s Matti Floman said the ideal solution would be universal memory. But given that is an unlikely development, what’s needed from his company’s standpoint are higher bandwidth for DRAM and non-volatile memory, new package solutions, lower power consumption, higher temperature tolerance, pre-developed scalable modules, and standard solutions.
He noted that Wide I/O is seen as a strong candidate for replacing DDR2 and DDR3 in high-end products. Mass memory, meanwhile, is moving toward NAND and embedded MultiMediaCard (eMMC).
Tags: 3D stacking, Applied Materials, double patterning, DRAM, EUV, Hynix, Imec, memory, Nokia, RRAM, Samsung, SRAM, Toshiba, Wide I/O