By David Lammers

(UPDATED) Intel Corp. may soon announce a 22nm technology which employs a FinFET architecture, rolling out 22nm microprocessors at the same time.

One source, who does not work at the microprocessor giant, said he believes Intel may use the vertical transistors for the cache SRAM transistors while adopting a planar approach to the logic devices. Another source said Intel will announce the 22 nm technology soon, including a FinFET architecture which includes several “surprises.”  A third source, Scott Thompson, a professor at the University of Florida who earlier worked in technology development at Intel, said he agrees with the speculation that Intel will use FinFETs, but doesn’t believe that Intel will use a hybrid FinFET/planar approach.

“My judgement is Intel will announce 22nm FinFETs for every single type of transistor, inclujding logic, SRAM, and analog,” Thompson said. “Based on a two year cycle, the Intel 22nm announcement is already a little late so I suspect Intel is having some difficulty with yields on a ‘FinFET everywhere’ approach for 22nm.”

Thompson said FinFETs present major challenges. FinFET height variation can lead to drive current variability, and making FinFETs on bulk wafers requires doping the fin in order to reduce leakage, he said.

Intel is expected to show working microprocessors based on the technology in the public rollout, which one source said will be made “very soon.” An Intel spokesperson responded to a request for information by saying the company “does not comment on rumors or speculation.”

Though Mark Bohr, Intel’s Director of Process Architecture & Integration, described a 22nm technology test vehicle SRAM in 2009, the company has “not provided any disclosures about the technology behind that,” the spokesperson said. For the last several months Intel has been expected to make a 22nm technology and processor rollout, and the spokesperson did not disagree that Intel has such an announcement on its schedule.

The hybrid FinFET/planar approach described by one source takes advantage of the higher SRAM cache density and Vmin control possible with a FinFET architecture, while preserving the basic planar design rules used to design the complex logic circuitry in Intel’s MPUs. Intel refers to FinFETs as a TriGate architecture, referring to the ability to control the channel on three sides with a wraparound gate design.

Thompson said he is “very sure” that Intel will not use a hybrid approach. “The complexity of the gate and spacer etch, and a dual metal replacement gate flow, mean that it is not practical or cost effective to manufacture a dual flow with planar in logic and a FinFET SRAM.”

Intel’s expected announcement, if confirmed, would mark the second time in less than five years that the company has moved ahead of the rest of the industry with a fundamental technology shift. In January 2007 Intel announced that it had incorporated a high-k/metal gate technology in its 45nm processors, rolling out several working processors based on the high-k gate stack at the same time.

Intel did not deliver any major papers at the International Electron Devices Meeting (IEDM) last December, leading to widespread speculation that it was on the verge of moving to a TriGate rollout.

Intel is expected to move to FinFETs well before its competitors, and the move will put pressure on other companies to finalize their own 20nm and 14nm roadmaps. Some companies are expected to adopt FinFETs, while others, including STMicroelectronics, have indicated they will adopt a fully depleted SOI technology at the 14nm node.

Last June, TSMC senior vice president S.Y. Chiang announced that the foundry plans to shift to a FinFET approach at the 14nm node, which will involve a major redesign of the design tools, legacy IP, and other elements in the foundry/fabless infrastructure. One source said the design effort to move to FinFETs will require fabless companies to get started now if they plan to use a TSMC 14nm FinFET technology. He speculated that TSMC would first offer a bulk planar 14nm offering and then later introduce a high-performance 14nm FinFET technology to its customers.

IBM has been giving conference presentations on both FinFET and ultra-thin-body silicon on insulator (UTB-SOI) transistors. GlobalFoundries said at its 2010 technology event that it would use a planar architecture for its 22/20nm offering, switching to a gate-last approach to high-k/metal gate deposition. GlobalFoundries will offer both SOI and bulk silicon to its customers, as it has in the past. It has not announced its 14nm direction.

In 2009, Intel said the  22nm test SRAM array included 364 million memory bits, using SRAM cells of 0.108 and 0.092 square microns. The 0.108 square micron cell was optimized for low voltage operation, while the 0.092 square micron cell was optimized for high density. The test chip included 2.9 billion transistors, Intel said.

This entry was posted on Tuesday, March 22nd, 2011 at 7:37 pm and is filed under News Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.