Heeding Manufacturing Rules In Design
By Ed Sperling
The quest to do more at the early stages of IC design to improve yield on the manufacturing side has largely consisted of a collection of independent steps, in part because of a silo mentality throughout the design process and in part because the market for integrated tools has been limited.
All of that is changing at 28nm, where complexity has reached a level that is well beyond the capabilities of the human mind to plan and adjust. And that complexity will only grow as geometries shrink to 22nm and beyond, 2.5D and 3D stacking begin rolling out, and as software becomes an increasing requirement for chip developers.
Mentor Graphics’ extension of its Calibre design for manufacturing (DFM) environment today is the first of what are expected to be a number of developments in this area, this one geared toward background design-rule checking (DRC) at the layout stage of a design. Layout itself used to be a fairly straightforward process several nodes ago, but with hundreds of millions of gates and a mixture of analog and digital logic, that’s no longer the case. Much of it cannot be automated, and strict design rules from foundries require much more attention much further forward in the design cycle.
“There are two times as many checks at 28nm for DRC as at 90nm,” said Joe Sawicki, vice president and general manager of Mentor’s Design-to-Silicon Division. “You also have to be much more precise about the yield effects.”
Increasing DRC checks and Moore's Law.
He said that one large company developed a chip with a large foundry that had a yield of about 8%. The problem turned out to be two nets bridging because of CMP dishing, but much of that could have been caught prior to the manufacturing with integrated design-rule checking.
“The key here is dynamic checking as you edit the layout,” said Joseph Davis, product marketing manager for Mentor’s Calibre Design Solutions. “Almost every tool has built-in DRC, but they’re not qualified by the foundries. So even if you have coverage for verification, it’s not correlated with the process. By adding this capability you can save weeks off a library design in a custom IC.”
The approach appears to have resonated with some chip developers, as well.
“Our designers are pushing the limits of the design rules to get the best analog performance,” said Ted Buchwald, a senior engineer at Mobius Semiconductor. “Having the signoff design rule checks in real time, while creating the layout, allows the designer to break the LVS-DRC-LVS loop. When a block is LVS-clean, it’s DRC-clean and ready for extraction. It completely changes the layout-verification-simulation flow and lets us focus on getting the best results possible. The tool was clearly designed by someone with first-hand analog layout experience in that it never seems to be in the way, but yet is always available to be used when and how the designer wants to use it.”
Tags: design-rule checking, Mentor, Mobius