By David Lammers

The biggest potential benefit of 3D lies in the ability to create heterogeneous solutions, speakers from IBM and Intel said at the 3D Cross-Cut Theme Workshop. Rather than try to cram multiple functions on an extremely large SoC die, with resultant yield impacts, design teams will create relatively small die in the appropriate process technology, experts said during the on-line conference, organized by the Focus Center Research Program.

Jerry Bartley, an IBM principal engineer, envisioned the day when teams of engineers would develop “systems on a stack,” rather than the system on a chip solutions created today. Heterogeneous stacks will create organizational issues. While semiconductor companies have employed a chip designer to do one thing and a package designer to do another, Bartley said “3D takes on a lot of the system-level attributes. The question arises: Is it a chip? Or a package? How do you integrate one chip guy with the other chip guy working on the strata above and below?”

Tanay Karnik, a principal engineer at Intel Research, said “it is better to have small die, implemented in different technologies” than to put every function on a monolithic piece of silicon. While TSVs add some costs, the total solution could be less expensive than a single large die. Large die sizes do not enjoy optimum yields, with a typical 15×15 mm die size having one-third the yield of a 10x10mm die in the overall chip industry, Karnik said.

Much of the attention in the 3D field thus far has focused relatively narrowly, on the significant bandwidth improvements between logic and memory, for example. Already, the industry is putting together homogenous die – Xilinx is linking multiple FPGAs with an interposer, and DRAM vendors are stacking DRAMs with vertical TSVs. Long range, they said, connecting heterogenous die will play the larger role.

“We can possibly get better RC delays if we don’t have to travel laterally,” Karnik said. “Some reduction of power consumption can be achieved. Possibly we can achieve lower costs. But the biggest benefit is in heterogeneous integration, separating the wireless, clocking, and I/O circuits from the digital. All can be separated and put on the best possible function,” Karnik said.

Bartley agreed, noting that “very short and wide interconnects” will boost bandwidth, and the lower capacitance from the shorter nets will reduce power. While those are oft-discussed benefits, Bartley said “modularity reuse with heterogeneous structures doesn’t get as much press.”

He envisioned the day when standards will allow die from different vendors to be quickly stacked. Companies will be able to purchase functions from a catalogue of stackable functions that can be purchased off the shelf and integrated. Once standards evolve, stacking may be done more simply, by pressing die together, for example.

Smaller vias and pitches will drive the industry’s ability to put more function on stackable structures. Certain functions will be spread across multiple layers in order to reduce the path length. Large IP blocks may be folded in half to reduce the distance, he suggested.

“Heterogeneous is where most of us envision 3D as being most valuable,” Bartley said. “Adding RF capability to logic, analog, MEMS, with logic and memory — those are the types of things we want to move towards. We can have all those functions mixed into one packaged device.”

In the medical area, IBM sees an opportunity to let MEMS steer a function around in the human body. “We can all get great value from having a mixed technology structure,” he said.

Challenges must be solved before the vision becomes reality. “Everything looks great,” Karnik said. “But there are no commercial products yet other than DRAM stacking. Why is 3D not a full-fledged product?”

Karnik listed several engineering issues, including:

•  Standards. While JEDEC standards are underway, a much wider standards effort is needed. “Different foundries are proposing different ways to do 3D,” Karnik noted, including how the die-to-die bonding steps are performed.

•  Yield issues. Memory redundancy must be addressed.

•  Thin wafers. The “paper-thin” wafers require an improved wafer-support system, he said.

•  Bonding and debonding. When the support wafer is debonded from the thin wafer, “bad things sometimes happen.”

•  Alignment. With dense die-to-die connections, alignment is critical. And with die warping, connecting all the TSVs is a challenge.

•  EDA. Reducing the keep out regions is one issue. Dealing with hot spots is another.

•   Testing. “With TSV processing, we lose visibility into various structures on the die. There is the known good die issue at the wafer level. We have to make sure both die are functioning.”

•  Power delivery.

•  Thermal. Hot spots “need to be misaligned” to avoid thermal problems.

Professor Sung Kyu Lim and Interconnect Focus Center (IFC) administrators at Georgia Tech, including center director Paul Kohl, organized the 3D Workshop.

This entry was posted on Monday, February 21st, 2011 at 3:41 pm and is filed under News Stories. You can follow any responses to this entry through the RSS 2.0 feed. You can leave a response, or trackback from your own site.