Partners Test UTB-SOI for Mobile Applications
By David Lammers
Using an ARM Cortex processor as a prototyping vehicle, a group of companies within the SOI Consortium has used 20nm Ultra Thin Body SOI technology to gauge the power and performance of fully depleted UTB-SOI compared for mobile applications. ARM, GlobalFoundries, IBM, STMicroelectronics, Soitec, and CEA-Leti cooperated on the project, using IBM’s Albany Research Center to fabricate the test wafers.
The partners tested fully depleted transistors created on ultra-thin-layer SOI wafers and found that performance was much higher than bulk silicon technology, said Horacio Mendez, executive director of the SOI Consortium. “Because of the buried oxide layer, there is much less capacitance, which means the transistors are much faster,” he said. The SOI Consortium did not divulge specific performance metrics, but said that the UTB-SOI technology delivered “an additional 80 percent gain beyond the traditional increase” of 20-30 percent achieved by moving to the next technology node.
Mendez also said the ARM prototyping core operated reliably at operating voltages down to 0.7 V, which he said is difficult to achieve on bulk CMOS.
In a previous test chip done last year, static power was relatively high, but Mendez said that was because the IBM 45nm transistors used then were optimized for high-performance systems. The 20nm devices used in the most recent test were optimized for mobile applications, where standby and dynamic power are critical. Mendez said the next step is to create test chips with both logic and SRAM. Test SRAMs made with the UTB-SOI technology have shown reliable operation at 0.65V, Mendez said.
Reducing the voltage of an SoC can impact the stability of the SRAM bit-cells. The SOI Consortium said early benchmarks on the UTB-SOI technology showed that reducing the SRAM operating voltage by 100-150 mV supported a 40 percent reduction in the memory power consumption, while maintaining the stability of the SRAM.
Asked about static power consumption in SOI, an IBM technologist said that partially depleted (PD) SOI historically has been targeted for high performance markets, including servers, game processors, PC processors, networking routers and switches. Those chips use transistors which are leakier than devices optimized for low-power systems. And because of the floating body effect in PD-SOI, reducing leakage is more challenging than in FD-SOI, where there is no floating body. In addition, a back gated FD-SOI device can adjust the back gate bias to reduce leakage further, adding yet another lever to control static power, he said.
Costs have been a stumbling block for widespread adoption of SOI in mobile systems. Soitec executives two years ago said leading-edge SOI wafers cost in the $800 range. Now, Soitec is offering volume prices in the $500 range for wafers with thin top silicon and buried oxide layers.
While Soitec remains the dominant SOI wafer supplier, Mendez said two high-volume wafer suppliers — Japan’s Shin Etsu Handotai (SEH), and MEMC, based near St. Louis — are ramping up their own UTB SOI wafer manufacturing operations. “The device makers have always been concerned about backup suppliers,” he said.
The cost question is not as simple as comparing a bulk wafer price with an SOI wafer price. The SOI Consortium claims that an undetermined number of mask layers can be subtracted by going to an SOI technology. Mendez declined to quantify the number of saved masks, saying that the consortium’s foundry partners consider that proprietary information. “Without going into details, I will just say that fully depleted SOI is very cost effective,” he said.
Halo, channel, and deep well implants, and shallow trench isolation (STI) steps are eliminated in fully depleted UTB-SOI, he said. Moreover, UTB-SOI can be enhanced with back biasing techniques that are not possible with the tall FinFETs. By etching through the thin BOX layer, a bottom gate can be created to control threshold voltages. Power can be saved by turning down the Vt when a chip is in operation and raising the Vt when it is in standby mode. Creating multiple threshold voltages in bulk is much more expensive, requiring implant steps and additional mask layers, Mendez said.
“Back biasing is something that has been going on in bulk for at least 10 years to reduce power. We can easily apply that to SOI once the BOX layer becomes thin,” he said.
According to Xavier Cauchy, Soitec’s digital aplications manager, and François Andrieu, a senior research engineer at LETI, the very thin silicon layer in UTB-SOI “enables the silicon under the transistor gate (the body of the transistor) to be fully depleted of charges.” That allows the gate to have tighter control over the full volume of the transistor body than is possible with a bulk CMOS transistor, especially at lower supply voltages. In addition, FD-SOI does not require doping in the channel, they said.
While an ultra-thin BOX involves a “somewhat more challenging process integration scheme,” Cauchy and Andrieu argue that there are several advantages to a thin BOX layer. The top silicon and BOX layers can be removed locally to reach the base silicon and co-integrate both SOI and bulk devices “with only a small step (20-30nm) between an SOI zone and an uncovered Bulk zone.”
One challenge is to control the variability of the silicon and buried oxide layers. In an article published at the Advanced Substrate News site, Christophe Maleville, general manager of the SOI business unit at Soitec, said by leveraging hydrogen implantation, Soitec’s Smart Cut technology now delivers on-wafer uniformity below the 1 nm range. Current wafers for FD SOI are being produced with 12nm top silicon and uniformity control at +/- 5 Å (0.5nm) for wafer-to-wafer distribution.
By improving the APC (advanced process control) further, Soitec expects to reach wafer-to-wafer uniformity of +/- 2 Å (0.2nm). “The roadmap is now in place for high-volume manufacturing,” Maleville said, producing wafers for FD SOI with top silicon uniformity control at +/- 5 Å (0.5nm).
