"..." - Il Prof
Deep Insights for Chip Builders
The move to 450mm wafers is under way, but nagging questions about ROI remain.…
DFM processes are no longer optional. They are now required by manufacturers to create efficient, high-performance chips…
Where do I know that guy from? And why is he here?…
Planar FD-SOI, FinFET, RF, memory and more—highlights of some great papers…
President Obama Visits Applied Materials
Tour grabs national headlines as President speaks out on jobs and manufacturing.…
The latest milestones and future trends for making MEMS a mainstream technology.…
Even ‘average’ is a good thing when it comes to wafer demand.…
Low-e Windows Built Using The Design Rules
How to create low e windows using design rules for the four energy bands.…
Fab Equipment Spending To Rise
Strong 2nd half pulls 2013 finally into positive territory, 2014 growth in double digits.…
SPIE Advanced Lithography 2013 - day 4
The last day of the conference gave the tool updates. So how is EUV progressing?…
Lessons From Past Architecture Wars
Why was Intel so successful when its very capable rivals were not? And can it maintain its lead?…
There's More To EUV Than Source Power
With a more powerful source, lithographers can use less-sensitive resists that are less prone to pattern collapse.…
In a question and answer format, Xavier Cauchy, digital applications manager at Soitec (xavier.cauchy@soitec.fr) and François Andrieu, senior research engineer at LETI, raise some of the technical issues surrounding fully depleted SOI technology.
The authors compare FD-SOI to FinFETs, describe how non-digital transistors can be handled, and provide a list of references for further reading.
Tags: Soitec