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Innovations for Transistor Scaling at PRiME 2016

Applied Materials will be presenting in five sessions at PRiME 2016, one of the largest international research conferences, being held October 2-7 in Honolulu, Hawaii.

Fabricating Advanced-Node, Multi-Patterning Schemes Demands Unprecedented Selectivity

Since the 1960’s, Moore’s Law has described the doubling of the number of transistors in an integrated circuit approximately every two years. This amazing technological feat requires the ability to generate structures at progressively smaller scales, which has traditionally been achieved with improvements in photolithography technology.

Contact Resistance and its Role in Limiting Transistor Performance

In logic devices, contacts and local interconnects (the first level of metal wires shown in Fig. 1) form the critical electrical pathways between the transistors and the rest of the circuit.

Finding the Killer Defects at 10nm and Beyond

Chipmakers’ vital need for higher inspection sensitivity continues to grow as they move to 10nm and beyond, and introduce complex structures and new materials into high volume manufacturing.

New CD SEM Advances 3D Patterning to See, Measure and Control 3D Devices

Ofer Adan, Global Product and Technology manager at Applied, reviews the tool’s technical innovations.

What’s in a Name? Innovation for Humanity

The project names Gooru, Nanoly, and Sanergy are intriguing. The fact these names represent efforts all over the world, from India to Latin America to Africa, peaks curiosity.

CD-SEM Sees Beyond Less Than 10 Nanometer Nodes

At the recent SPIE Advanced Lithography conference, my keynote presentation focused on how improvements in metrology, multi-patterning techniques and materials can enable 3D memory and the critical dimension (CD) scaling of device designs to sub-10nm nodes.

Materials Innovation Key To Enabling Next-Generation Mobile Devices

The next cool gadgets will require new materials, new technology nodes and new architectures.