By Ofer Adan
At the recent SPIE Advanced Lithography conference, my keynote presentation focused on how improvements in metrology, multi-patterning techniques and materials can enable 3D memory and the critical dimension (CD) scaling of device designs to sub-10nm nodes. At these nodes, the growing complexity of designs make it extremely challenging for current photolithography tools to create viable patterns. And further complicating patterning and metrology is 3D integration, which has contributed to the steady growth in the number of parameters to measure and control.
For years, a CD scanning electron microscope, or CD-SEM, has been used to take measurements by sending out an electron beam that interacts with the material being scanned, and then sends back signals, which are mapped by the equipment. Today, there are serious questions about what happens at sub-10nm where the CD-SEM or any other metrology equipment must account for many more film layers, higher aspect ratios, narrower pitches and the contours and shapes of 3D architectures.
To answer skeptics and underscore improvements being made to CD-SEM, it would be helpful to highlight some key challenges and results presented that demonstrate the extendability of this metrology technology. Examples include logic vias, overlay complexity, and extremely high aspect ratio (HAR) memory contacts.
Figure 1 represents the challenge of measuring and monitoring via-in-trench bottom CD and alignment. As the diagram shows, the via edges and its placement must be precise to ensure proper connections between underlying and overlaying metal layers. The via on the right does not align with the copper line below it, which will affect conductivity between layers. The SEM images in the bottom show the difference between vias that are off-set and aligned. Both critical image sets were achieved using backscattered electron (BSE) imaging, which is becoming a viable technique for metrology. This case demonstrates using CD-SEM remains effective as a metrology and alignment technology in this complex, multi-step process.
Spotting problems with via alignment at sub-10nm cannot be done without improvements such as increasing SEM resolution as current CD-SEM technologies are not precise enough. Today with new developments we’re starting to use thousands of kilovolts to “see through” to the lowest layers since it is necessary to align down through the BARC (bottom anti-reflective coating), through the hardmask and to the metal, the contact or the Fin. Figure 2 shows the higher resolution image capabilities advanced CD-SEM can provide while seeing through materials in comparison to ordinary SEM.
Figure 3 shows in the top SEM image how properly etched deep contact holes pass completely through the material, while the ones pictured below it don’t and would need to be corrected before deposition. This result of being able to image the HAR contact holes was achieved using improved detection and collection techniques. Through a combination of employing BSE signals and enhanced filtering of signals to only those electrons that hit the surface of the bottom and come back up, it’s possible to image the bottom and fidelity of HAR holes.
Finally, in my keynote I also referenced work presented by colleagues during the conference on FinFET*, and Silicon Nanowire 3D** metrology. All these topics share a common theme of a transition from lithography limited 2D scaling to metrology and materials enabled 3D patterning.
Fortunately, advances in metrology are addressing major scaling issues. For sub-10nm structures and 3D memory, optimized, better SEMs with sharper focus, more sophisticated image and data acquisition methods and shape-sensitive, physics-based modeling and simulation are required. The future also requires using a combination of different metrology technologies including CD-SEM, CD atomic force microscopy (AFM), and transmission electron microscopy (TEM).
* X. Zhang, et al., Addressing FinFET challenges in 1Xnode by image-based 3D metrology using CD-SEM tilt beam, SPIE 2014.
** S. Levi, et al., CD-SEM AFM hybrid metrology for the characterization of gate-all-around silicon nanowires, SPIE 2014.