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Archive for December, 2012

Interconnect Troubles

Thursday, December 13th, 2012

By Mehul Naik
These days, transistor scaling is driving some of the most exciting innovations in device architecture and getting lots of attention as a result. What may be less obvious is the cascading effect transistor scaling is having on the interconnect. The biggest challenges result directly from pitch reduction required to support the increasing functionality. These include poor pattern integrity, increased RC delay, and inferior reliability.

Pattern integrity always has been important, but never to the degree that we face now. Already, the industry has moved to hard mask-based process flows for compatibility with double patterning at and below the 2x nm node. TiN is the most commonly used. Its high selectivity during low-k etch is an advantage, but the high compressive stress of these masks combined with the low mechanical strength of ultra-low-k (ULK) materials can cause buckling of interconnect lines. Lowering TiN hard mask stress is the logical solution to relieve line buckling.

Unfortunately, it is not as simple as that. Lowering the stress in conventionally deposited TiN reduces the density of the film and that leads to poor dielectric etch selectivity. We need to create a lower-stress TiN without affecting the density. The solution lies in advanced PVD technology that generates greater plasma density that makes possible low-energy deposition with less bombardment. In this way, a high-density, low-stress hard mask can be created with all the attendant benefits of no buckling, high selectivity, and scalability.

As for RC delay, the 14nm node is likely to be the inflection point beyond which copper resistivity increases exponentially. The reason lies in greater scattering at sidewalls, surfaces in copper lines with diameters less than 40nm. Just imagine what the effect will be at the 14nm node, where metal line widths will shrink to as little as 22nm.

Maximizing copper volume and grain size while minimizing scattering will be key in keeping resistance in check. Thickness of high resistance barrier-liner layers together with interfacial effects, have an increased contribution to the overall resistance of the line.

All things being equal, up to 35% lower resistance can be achieved by thinning liners from 3nm to 1nm. Recently developed copper reflow techniques can produce a larger grain size, but the scattering issue is going to require more disruptive and high-risk approaches. One possibility is a dielectric-copper interface. For this to be viable though, a new materials system will be required, such as self-forming barriers. And, new fill techniques will be needed that do not require a conducting substrate.

Advanced patterning has substantially raised the reliability stakes. While self-aligned double patterning can be used to avoid line-to-line overlay issues, via patterning still requires litho-etch-litho-etch. Line-via shorting and TDDB will become key limiters. These means that self-aligned via (SAV) schemes will be required. But although SAV may resolve line-via overlay issues at the same level, level-to-level alignment scaling is going to remain a serious challenge. Interfaces and bulk low-κ materials will have to be dramatically improved to satisfy TDDB requirements for the ≤10nm node.

Shortened electromigration (EM) lifetimes are another challenge. In this case, CVD-based selective metal capping has yielded encouraging results in preventing diffusion at the copper-dielectric barrier interface; studies show up to 80X improvement in EM. This is a scalable solution as the metal does not require aggressive pre- or post-cleaning; does not increase resistivity by diffusing into the copper; and is ≤2.5nm thick, which minimizes the impact on capacitance.

—Mehul Naik is a distinguished member of the technical staff at Applied Materials.

Interconnect Performance In The Spotlight

Tuesday, December 4th, 2012

By Richard Lewington
Are you going to be in the San Francisco area on December 11th?

We’re hosting a forum to explore the path that interconnect technology must take to keep pace with transistor scaling and the transition to new 3D architectures.

Transistors get all the attention these days as the savior of Moore’s Law. But there’s no point making transistors faster if the wires between them – interconnects – can’t keep up.

The 14 nanometer node is expected to be an inflection point for the chip industry, beyond which the resistivity of copper interconnects will increase exponentially and may become a limiting factor in chip design.

The discussion will address critical questions for the semiconductor industry, including the possibility of replacing copper as the material of choice for interconnect structures. If not, will new circuit designs and system architectures be able to address future limitations in interconnect performance? The complexity of multi-patterning and EUV lithography timing may also impact chipmakers’ interconnect pitch scaling roadmaps.

Experts from across the industry will provide insights on these critical issues in a panel titled “Interconnect Performance – Overcoming the Impact of Transistor Scaling.”

Click here to register for what promises to be an illuminating and lively discussion. We look forward to welcoming you!

Klaus Schuegraf, Ph.D. Vice president and chief technology officer, Silicon Systems Group, Applied Materials, Inc.

Robert Aitken, Ph.D. Fellow, ARM Holdings, Ltd.
Jon Candelaria Director, interconnect and packaging sciences, Semiconductor Research Corp.
Dinesh Somasekhar, Ph.D. Senior scientist, Intel Corp.
Zsolt Tokei, Ph.D. Program director, nano interconnects, IMEC
Mehul Naik, Ph.D. Distinguished member of technical staff, Applied Materials, Inc.
Douglas Yu, Ph.D. Senior director, backend R&D, TSMC, Ltd.
David Lammers (moderator) Contributing editor,

Hotel Nikko
222 Mason Street, San Francisco, CA 94102

Tuesday, December 11, 2012

5:00pm – 6:15pm Registration and Reception
6:15pm – 7:40pm Panel Discussion
7:40pm – 8:00pm Beverages/Social

—Richard Lewington is a writer in Applied Materials’ Technical Communications group.

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