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How New Materials Can Solve Contact Resistance

January 25th, 2017

By Mike Chudzik

Most connected computing devices today use 3D FinFET transistors enabled in part by technology innovations from Applied Materials. The challenging transition to FinFETs was essential to continue Moore’s Law scaling. But as usual, when one problem is resolved others loom. One of the most serious of these is increased contact resistance. I briefly touched on this in a previous blog.

So why is the contact so critical and challenging? It is one of the smallest structures in the device that connects close proximity transistors to each other and to the upper levels of copper interconnect wiring, as shown in figure 1. The industry has spent years boosting transistor performance by changing materials and architectures. Interconnect wiring has also been optimized to support the transistor. Squeezed in between, the contact controls the flow of signals from the transistors and interconnects to the external world. If the conductivity of this electrical connection isn’t good, it will bottleneck the flow of current and limit performance.

That’s why mapping out the future for the contact is paramount. Pretty much every chipmaker is working aggressively to alleviate this issue. They understand if it’s not resolved then it won’t matter what else is done with the device to try and boost performance.

To mitigate resistance, alternative liner/barrier technologies (more on this in the blog by my colleague Jonathan Bakke) and moving to multiple levels of thinner contacts at 10nm are being implemented. This progression in design changes is illustrated in figure 2. But even with these innovations, scalability at 7nm and beyond will be extremely challenging.
For more than 25 years the main electrical conducting material in the contact has been tungsten (W). But with scaling, there is less volume left in the contact for W, making it increasingly difficult to get the current through. A promising option moving forward for the contact is to use a new material. Researchers are experimenting with cobalt (Co) to replace W.
Co offers major advantages as a contact replacement material to increase the volume of the contacts as they are scaled. It doesn’t require the thicker barrier layers like W does, which opens up more room for the contact (fill) material. Plus, it’s not just the deposition step for the bulk fill involved – there is annealing as well. Co has a higher thermal budget making it possible to anneal, which provides a superior, less granular fill with no seam and thus lowers overall resistance and improves yield.
Applied is focused on enabling customers to reduce contact resistance. While replacing W with Co is a crucial transition, there’s much more involved to make a robust contact. In a future blog, I’ll take a look at all the steps and technologies involved to make a really low-resistivity 7nm contact.

Innovations for Transistor Scaling at PRiME 2016

September 29th, 2016

By Applied Blog

Applied Materials will be presenting in five sessions at PRiME 2016, one of the largest international research conferences, being held October 2-7 in Honolulu, Hawaii. This important conference hosted by the Electrochemical Society (ECS), the Electrochemical Society of Japan (ECSJ) and the Korean Electrochemical Society (KECS) is convened every four years. Applied’s talks will focus on inflections in transistor scaling, in particular the epitaxy technologies and materials innovations required for manufacturing advanced devices.

One historic change that has taken place in transistor design to address device scalability is the move to the multi-gate architecture of the FinFET, which enables the increase of the gate length and dramatically improves electrostatic performance. Beyond FinFET, the GAA (Gate All Around) device structure is one of the most promising paths for offering another disruptive leap in transistor scaling. Epitaxy is playing an increasingly critical role for enabling these device architectures, which have much more complex integration schemes and tighter process control requirements than planar devices.

In the past decades, germanium (Ge), silicon germanium (SiGe) and III-V semiconductor materials have garnered intense interest due to their superior electronic and optical properties and great potential to improve device performance. Silicon germanium epitaxial layers can act as a virtual substrate for growth of tensile or compressively strained layers that can serve as N and PMOS channels supporting continued scaling of Si CMOS technology. III-V materials compared to Si have about 10 times higher mobility and 2-3 times faster injection speed. CMOS devices can benefit from higher mobility and injection speed to improve operation frequency, current and power consumption, and to reduce short channel effect.

Strain Relaxed Silicon Germanium Buffer Layers: From Growth to Integration Challenges

A. Dube, Y. C. Huang, B. Cherian, K. Nafisi, H. Chung, and S. Chu (Applied Materials)
Tuesday, October 4, 2016, 2:00pm

Group IV Epitaxy Applications for Enabling Advanced Device Scaling

B. P. Colombeau, M. Bauer, B. S. Wood, H. Chung, J. Hebb, Y. C. Huang, X. Tao, S. Chopra, A. Dube, M. Chudzik, and S. Chu (Applied Materials)
Wednesday, October 5, 2016, 2:40pm

Building III-V Devices onto Large Si Wafers

X. Y. Bao, Z. Ye, D. Carlson, and E. Sanchez (Applied Materials)
Wednesday, October 5, 2016, 6:00pm

Optimal Target Functions for Epitaxy in New Channel Applications Such As Horizontal Gate All Around (hGAA) Device Architectures Using NanoSheets or Nanowires

M. Bauer (Applied Materials)
Friday, October 7, 2016, 8:00am

Growth and Etch Forms of Germanium Microcrystals on a Silicon Oxide Substrate

Y. C. Huang, M. P. Cai, H. Zhou, and H. Chung (Applied Materials)
Friday, October 7, 2016, 1:40pm

Applied is also hosting a reception at the event. You can register here.

We hope to see you there!

eBeam Applications

July 18th, 2016

By Dror Shemesh

eBeam technology is used in a variety of process control and monitoring applications to help optimize the quality and stability of device fabrication as discussed in the video and summarized in the below infographic.

Click here to watch the tutorial.

Fabricating Advanced-Node, Multi-Patterning Schemes Demands Unprecedented Selectivity

July 1st, 2016

By Matt Cogorno

Since the 1960’s, Moore’s Law has described the doubling of the number of transistors in an integrated circuit approximately every two years. This amazing technological feat requires the ability to generate structures at progressively smaller scales, which has traditionally been achieved with improvements in photolithography technology.
Delays in developing commercially viable EUV lithography, however, have caused device manufacturers to shift the focus away from lithography-based scaling in favor of integration schemes that take advantage of materials properties to define tiny patterns needed to create modern electronic devices. These so-called self-aligned multi-patterning schemes require that one material be completely and cleanly removed without damaging others (Fig. 1). The ability to achieve this is referred to as extreme selectivity.

Fig. 1. The minute dimensions of multi-patterning schemes require extreme selectivity to completely remove the target material (dark blue silicon above) without damaging others (grey dielectric spacers above).

Self-aligned multi-patterning poses several issues for traditional wet etch. Wet chemistry doesn’t etch certain crystal planes of silicon, so a wet process will leave silicon residues behind, which causes defects in the pattern. Because the budget for loss of the dielectric material forming spaces in the pattern is getting much tighter, extreme selectivity is essential to prevent such loss and preserve critical dimension.
In my next post, I’ll introduce a disruptive etch technology that delivers the extreme selectivity needed for these patterning schemes as well as for further scaling of current FinFET, 3D NAND, and DRAM designs. This radically different approach will also strengthen the feasibility of fabricating gate-all-around transistors and give chip developers more freedom to create similarly innovative designs in the future.

Contact Resistance and its Role in Limiting Transistor Performance

June 2nd, 2016

By Jonathan Bakke

In logic devices, contacts and local interconnects (the first level of metal wires shown in Fig. 1) form the critical electrical pathways between the transistors and the rest of the circuit. Low resistivity is therefore crucial for robust and reliable device performance. Consequently, low-resistivity CVD tungsten (W) has historically been used for logic contact and local interconnect fill.

As devices have scaled downward, numerous innovations have enhanced transistor performance, but the accompanying scaling of interconnect dimensions has reached the point at which contact resistance is becoming an obstacle to realizing optimum transistor performance. This is because as the cross-section of the interconnect decreases, a growing proportion of the volume is occupied by metal liner, barrier and nucleation layers, leaving less volume for the conducting W fill.

To date, high-resistivity TiN has been predominantly used as an adhesion layer for CVD W and to block fluorine penetration during the bulk fill process. W does not grow directly on TiN; thus, it requires deposition of a nucleation layer before the fill step. As logic devices scale through the 10nm node and beyond, the maximum critical dimension of the local interconnect will be <25nm. This leaves <12nm for low-resistance W fill, which results in high overall contact resistance (Fig. 2). In addition, the interfaces between each of the layers add to the overall resistance of the contact.

In my next blog post, I’ll explain how materials engineering is reducing contact resistance, making it possible to extend tungsten technology to next-generation devices.

Visit the Applied Materials web site to learn more about this technology.

Examining Emerging Memory Technologies and 3D Architectures at IITC

May 23rd, 2016

By Dr. Er-Xuan Ping

Emerging memory technologies and the shift to 3D architectures have the potential to overcome current memory limitations in speed, power consumption, reliability and cost to support future data-centric computing trends. And, as evidenced by the considerable investments being made in the various new memories — PCRAM, STTRAM, OxRAM and CBRAM, and 3D architectures such as 3D XPoint™ memory and 3D ReRAM, there is broad interest and competition to develop these technologies for future applications and in particular, for the commercial Internet of Things (IoT) market.

I’ll be giving an invited talk at the International Interconnect Technology Conference (IITC) in San Jose this week to review the status of these new memories and highlight the integration and high volume manufacturing challenges. Below is a brief outline of some of the interconnect issues and the need for new materials.

The first thing to know about emerging non-volatile memories (NVM) is they operate very differently from the widely used and highly commercialized DRAM, SRAM and flash memories (NAND and NOR). Emerging memories are based on physics mechanisms rather than charge-based mechanisms. For example, instead of manipulating electrons, PCRAM uses material phase change generated by electrically induced heat that yields different resistances. STT-MRAM uses spin-polarized current to change the magnetization of magnetic materials so that the resistance of two magnetic layers changes to high and low when the magnetization between them is parallel or anti-parallel, resulting in a phenomenon known as the giant magnetoresistive effect. And, OxRAM and CBRAM use local oxygen vacancy or metal ions that drift in and out of a narrow path pre-constructed by the electrical field and current.

As non-volatile storage technologies using no-charge based mechanisms, the new memories exhibit much faster operation speeds and greater erase/write cycle endurance than NAND flash (NVM). Another advantage is they can be readily integrated using standard CMOS Cu BEOL technology, making them very appealing for high-volume manufacturing.

One of the most important parameters of NVM is data retention. This attribute is critical for automotive control and future IoT applications, as these involve extreme operational conditions, such as high temperatures, current flash memory is unsuitable. To achieve high-temperature data retention and prevent data loss, it has been found that high program energy is required (typically current density in the range of 3-10MA/cm2). The problem with this current density is it’s extremely challenging for commonly used metal wires and contacts (Cu and W) as it approaches the electro-induced migration threshold.

Another issue is the need for high-density memory to scale to the 20nm dimension to be competitive. At this scale, the metal requirements become more stringent as scattering impacts the efficient flow of electrons. This condition worsens as the small wires scale further. Innovations new conducting materials are needed that mitigate scattering loss as features scale to sub-20nm is needed, as well as solutions that reduce material loss during integration from such effects as oxidation and plasma damage.

Typically, the new NVMs operate between the nanosecond (STTRAM, OxRAM) and microsecond (CBRAM, PCRAM). For these memories, parasitic capacitance is a larger issue to RC delay than for flash NVM. To ensure high-speed operation, implementing a range of new materials is expected, including magnetic and phase change materials — both of which are very different from traditional Si IC materials and low k materials. Integrating the new materials will require some process changes. Additional parasitic impact can still emerge as may be the case with the OxRAM filament as its size is determined by the amount of atom drift and can be disturbed by a discharge of parasitic capacitance.

Cost is a historical factor driving memory roadmaps. And the costs associated with patterning, as well as reaching limitations in operational basics and in the number of electrons, have made continued 2D scaling untenable. Scaling vertically into the third dimension, for example with 3D NAND and 3D XPoint memory, reduces patterning requirements and allows the industry to continue on its traditional cost reduction curve.

However, the high aspect ratio structures of 3D designs produce new deposition and etch challenges. To achieve further overall cost reductions, metal wires are being shared by multiple memory cells, but this adds to the integration challenge as the typical damascene process is not easy to implement in 3D architectures. Metal material sensitivity to etching and dielectric encapsulation is increasing dramatically, creating the need for material changes. This is especially important for the 3D XPoint technology where an x-y grid process defines an individual device comprising a selector, memory and metal wire as either bit line or word line.

I hope this preview of my talk is interesting and informative.

Applied Materials Hosts Memory Panel Discussion at IEEE IMW

May 4th, 2016

By Gill Lee

New types of Storage Class Memory (SCM) are emerging that may offer faster performance and better endurance than NAND. While the new SCM technology can offer read performance approaching that of DRAM and much faster write performance than NAND, it poses new materials and process execution challenges as well as unresolved questions related to system design and memory management. Can the new SCM replace embedded applications? Will it become a commodity-type memory? Can it be cost-competitive with DRAM or NAND? What applications might be best suited for SCM?

These questions and more will be addressed during a panel discussion titled SCM: Technical and Commercial Challenges chaired by Applied Materials as part of the eighth IEEE International Memory Workshop (IMW) at the Paris Marriott Rive Gauche Hotel on May 16. We are delighted that distinguished speakers from several memory technology leaders including Intel, Samsung, SK hynix and Western Digital will participate to exchange opinions in what we anticipate will be a highly informative discussion.

This IEEE conference is a leading forum for discussions among members of the international memory community on memory processes and design technologies, applications, market needs and strategies, and is well attended by our customers in both memory and logic.

Hope to see you there!

Finding the Killer Defects at 10nm and Beyond

March 29th, 2016

By Karen Krivaa

Chipmakers’ vital need for higher inspection sensitivity continues to grow as they move to 10nm and beyond, and introduce complex structures and new materials into high volume manufacturing. Today’s fabs require advanced process control technologies that deliver statistically significant killer defect detection to shorten ramp times and improve production yields.

One major challenge as design rules shrink is the optical signals received from defects are becoming smaller and the separation between killer and nuisance defects is harder to achieve as process complexity grows. Distinguishing between defects of interest and nuisances relies heavily on advanced imaging techniques.

To address this scaling challenge, Applied’s UVision 7 optical inspection tool uses Marker™ technology which integrates simultaneous dual brightfield and greyfield channel optical information with CAD and FAB inputs for optimizing the separation of killer defects from nuisance defects in complex 3D designs. Shirley Hemar from Applied’s Process Diagnostics and Control Group reviews the tool’s technical innovations and capabilities.

View Applied Materials’ video here.

3D NAND Goes Mainstream

August 26th, 2015

By Brad Howard

Earlier this month, I participated in a panel discussion with colleagues from Cypress, Micron, Samsung and SK Hynix at the Flash Memory Summit 2015 in Santa Clara, California.

Over the past year, the industry has made great strides in bringing 3D NAND closer to becoming a mainstream technology. For example, at the summit, Samsung unveiled the world’s largest SSD – a 16TB drive, which is also larger than any conventional hard disk drive on the market today. This is a strong indication that SSDs using 3D NAND flash are well on the way to becoming the price and capacity leader in the expanding enterprise storage market.

However, there is still much work to be done if 3D NAND applications like Samsung’s 16TB drive are to make their way into the cost-sensitive consumer market. This became apparent during the audience Q&A, when the panel was asked how 3D NAND can continue to cost-effectively scale, particularly with a complex production process.

In my view, many of the scaling challenges are being met thanks to innovations in 3D NAND manufacturing.

For example, we’ve learned that at very high aspect ratios (more than 48 device layers), the ability to maintain etch performance from the top of the feature down to the bottom is getting much harder when using wet etch processes. Wet processing these very high aspect ratio features can actually damage them, causing them to topple or get pulled toward one another.

There is also the challenge of making the device within the feature that requires selectively removing one material with respect to the other to create a three-dimensional structure as shown in the image below. These combined challenges can be solved by using isotropic dry etching solutions that achieve high selectivity, low damage to the materials, and provide much more precise top-to-bottom uniformity.

During my opening remarks on the panel, I also presented the image below to highlight how increasing aspect ratios that result from adding more and more layers to 3D structures, like those used in 3D NAND, create issues for atomic layer deposition (ALD) saturation.

While ALD provides precise conformal and uniform layers, it is still challenging to saturate all the surfaces of the structures on the chip. And, as device layers and feature complexity increase, more surface area is created, which exacerbates the issues for saturated coverage. Advances in high-performance ALD technology can address the industry’s need for complete film coverage without compromising productivity.

Despite the increasing complexities of 3D NAND scaling, I foresee a long future for this technology if the etch control and deposition steps can be broken down into manageable chunks. This is part of technology development that, as an industry, we’re used to and can address. Our ability to keep innovating and pushing process technologies will help drive the scaling roadmap.

50 Years of Moore’s Law

April 17th, 2015

By Dr. Randhir Thakur

For 50 years, Moore’s Law has served as a guide for technologists everywhere in the world, setting the pace for the semiconductor industry’s innovation cycle. Moore’s Law has made a tremendous impact not only on the electronics industry, but on our world and our everyday life. It led us from the infancy of the PC era, through the formative years of the internet, to the adolescence of smartphones. Now, with the rise of the Internet of Things, market researchers forecast that in the next 5 years, the number of connected devices per person will more than double, so even after 50 years we don’t see Moore’s Law slowing down.

As chipmakers work tirelessly to continue device scaling, they are encountering daunting technical and economic hurdles. Increasing complexity is driving the need for new materials and new device architectures. Enabling these innovations and the node-over-node success of Moore’s Law requires advancements in precision materials engineering, including precision films, materials removal, materials modification and interface engineering, supported by metrology and inspection.

Though scaling is getting harder, I am confident Moore’s Law will continue because equipment suppliers and chipmakers never cease to innovate. As we face the increasing challenges of new technology inflections, earlier engagement in the development cycle between equipment suppliers and chipmakers is required to uncover new solutions. Such early and deep collaboration is critical to delivering complex precision materials engineering solutions on time. In fact, in the mobility era, earlier and deeper collaboration across the entire value chain is essential (applications, system/hardware, fabless, foundry/IDM, equipment supplier, chemical supplier, component supplier, etc.) to accelerate time to market and extend Moore’s Law.

Today, new 3D architectures, FinFET and 3D NAND, are enabling the extension of Moore’s Law. Dense 3D structures with high aspect ratios create fundamental challenges in device manufacturing. Further, the industry has shifted much of its historical reliance from litho-enabled scaling to materials-enabled scaling, requiring thinner precision films with atomic-scale accuracy. The emphasis on thin conformal films, which can be 2000 times smaller than a human hair, makes it increasingly critical to engineer film properties and manage film interactions between adjacent film surfaces. Selective processing is also a growing requirement, particularly for the deposition and removal of films. We expect more selective applications beyond Epitaxy and Cobalt liner deposition. There will also be a major expansion of new materials in addition to the key inflection of high-k metal gate that helped to reduce power leakage issues associated with scaling.

Gordon Moore’s prediction that ignited an industry will continue to influence our way of life through a combination of architecture and material changes. New process designs and new ways to atomically deposit materials are needed. More processes will be integrated on the same platform without vacuum breaks to create pristine interfaces. As an equipment supplier, we have to manage longer R&D cycles to support the industry’s roadmap, and plan for faster ramp and yield curves. Of utmost importance is staying close to our customers to ensure we deliver solutions with the desired economic and technical benefits.

Looking at the electronics industry from where it is today out to 2020, many more devices will be in use, the world will be more connected and, particularly in emerging markets, there will be greater consumer appetite for more products with advanced features. Given these transformations and demand, I think the growth and excitement in our industry will continue for many more years, thanks to Moore’s Law.

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